PEB 3086 F V1.4 Infineon Technologies, PEB 3086 F V1.4 Datasheet - Page 68

• Manufacturer Part Number: PEB 3086 F V1.4
• Description: IC ISDN ACCESS CTRLR TQFP64
• Manufacturer: Infineon Technologies
• Series: ISAC™r

Specifications of PEB 3086 F V1.4

• Function: Subscriber Access Controller
• Interface: HDLC, IOM-2, ISDN, Parallel, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: D-Channel Access Control and Priority Handler, Monitor Channel Handler, Non-Auto Mode, Transparent Mode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3086FV1.4XT; PEB3086FV14NP; PEB3086FV14XP; SP000007571; SP000007572

Note: The IOM-2 interface is adaptive. This means in LT-S/NT and LT-T mode other
Note: i = input; o = output;
Data Sheet
frequencies for BCL and DCL are possible in the range of 512-4096 kHz
(DCL) and 256-2048 kHz (BCL). For details please refer to the application
note “Reconfigurable PBX”.
For all input clocks typical values are given although other clock frequencies may
be used, too.
1) The modes TE, LT-T and LT-S can directly be selected by strapping the pins
MODE1 and MODE0. The mode can be reprogrammed in TR_MODE.MODE2-0
where NT and Intelligent NT can be selected additionally. In Int. NT mode MODE0
selects between NT state machine (0) and LT-S state machine (1).
2) In TE mode the S transceiver can be disabled (TR_CONF0.DIS_TR=1) so the
IOM clocks become inputs and with IOM_CR.CLKM the DCL input can be
selected to double clock (0) or single bit clock (1).
3) ACFG2.A5SEL=1 selects the FBOUT function (derived from IOM clocks) which
provides an FSC/BCL output clock if clocks are present on IOM.
4) The number of IOM channels depends on the DCL clock, e.g. with
DCL=1536 kHz 3 IOM channels and with DCL= 4096 kHz 8 channels are
available.
5) In LT-T mode the 1536 kHz output clock on SCLK is synchronous to the S
interface and can be used as input for the DCL clock.<
6) The direction input/output refers to the direction of the B- and D-channel data
stream across the S-transceiver. Due to the capabilites of the IOM-2 handler the
direction of some other timeslots may be different if this is programmed by the host
(e.g. for data exchange between different devices connected to IOM-2).
68
Description of Functional Blocks
PEB 3086
2003-01-30
ISAC-SX