DS21Q55 Maxim Integrated Products, DS21Q55 Datasheet - Page 12

• Manufacturer Part Number: DS21Q55
• Description: IC TXRX QUAD T1/E1/J1 SCT 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q55

• Function: Transceiver
• Interface: E1, J1, T1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Includes: BERT Generator and Detector, Dual HDLC Controllers
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

DS21Q55 Quad T1/E1/J1 Transceiver
1.1 Functional Description
The DS21Q55 is a software-selectable quad MCM device for T1, E1, or J1 short-haul and long-haul
applications. Each is composed of an LIU, framer, HDLC controllers, and a TDM backplane interface,
and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS21Q55
is software compatible with the DS2155 single chip transceiver. The DS21Q55 is pin compatible with the
DS21Qx5y family of products.
The LIU is composed of transmit and receive interfaces, as well as a jitter attenuator. The transmit
interface is responsible for generating the necessary waveshapes for driving the network and providing
the correct source impedance depending on the type of media used. T1 waveform generation includes
DSX-1 line build-outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 waveshapes for both 75Ω coax and 120Ω twisted cables. The receive interface
provides network termination and recovers clock and data from the network. The receive sensitivity
adjusts automatically to the incoming signal and can be programmed for 0 to 43dB or 0 to 12dB for E1
applications and 0 to 30dB or 0 to 36dB for T1 applications. The jitter attenuator removes phase jitter
from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz
MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications)
and can be placed in either transmit or receive data paths. An additional feature of the LIU is a CMI
coder/decoder for interfacing to optical networks.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane
interface section. The framer inserts the appropriate synchronization framing patterns, alarm information,
calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI
line coding. The receive-side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the
data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock/data and
frame-sync signals to the backplane interface section.
Each transceiver has two HDLC controllers. The HDLC controllers transmit and receive data through the
framer block. The HDLC controllers can be assigned to any time slot, group of time slots or a portion of a
time slot. The HDLC controllers can also be assigned to the FDL (T1) or Sa bits (E1). Each controller has
128-byte FIFOs, thus reducing the amount of processor overhead required to manage the flow of data. In
addition, built-in support for reducing the processor time is required in SS7 applications.
The backplane interface provides a versatile method of sending and receiving data from the host system.
Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1
network to a 2.048MHz, 4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also
manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up
to eight transceivers to share a high-speed backplane.
The parallel port provides access for control and configuration of all the DS21Q55’s features. The
extended system information bus (ESIB) function allows up to eight transceivers (or 2 DS21Q55s) to be
accessed by a single read for interrupt status or other user-selectable alarm status information. Diagnostic
capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down
code generation and detection.
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