DS21Q55 Maxim Integrated Products, DS21Q55 Datasheet - Page 116

IC TXRX QUAD T1/E1/J1 SCT 256BGA

DS21Q55

Manufacturer Part Number
DS21Q55
Description
IC TXRX QUAD T1/E1/J1 SCT 256BGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS21Q55

Function
Transceiver
Interface
E1, J1, T1
Number Of Circuits
4
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Includes
BERT Generator and Detector, Dual HDLC Controllers
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power (watts)
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS21Q55
Manufacturer:
DS
Quantity:
959
Part Number:
DS21Q55
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q552
Manufacturer:
DS
Quantity:
7
Part Number:
DS21Q552
Manufacturer:
DALLAS
Quantity:
319
Part Number:
DS21Q552
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q552+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q552BN+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q552N+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q554
Manufacturer:
DS
Quantity:
20
Part Number:
DS21Q554
Manufacturer:
AD
Quantity:
301
Part Number:
DS21Q554
Manufacturer:
DALLAS
Quantity:
20 000
Part Number:
DS21Q554B+
Manufacturer:
MAXIM/美信
Quantity:
20 000
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a change of
state to a valid BOC. The setting of this bit prompts the user to read the RFDL register.
Bit 1/Receive FDL Match Event (RMTCH). Set whenever the contents of the RFDL register matches RFDLM1
or RFDLM2.
Bit 2/TFDL Register Empty Event (TFDLE). Set when the transmit FDL buffer (TFDL) empties.
Bit 3/RFDL Register Full Event (RFDLF). Set when the receive FDL buffer (RFDL) fills to capacity.
Bit 4/RFDL Abort Detect Event (RFDLAD). Set when eight consecutive 1s are received on the FDL.
Bit 5/BOC Clear Event (BOCC). Set when 30 FDL bits occur without an abort sequence.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive BOC Detector Change-of-State Event (RBOC)
Bit 1/Receive FDL Match Event (RMTCH)
Bit 2/TFDL Register Empty Event (TFDLE)
Bit 3/RFDL Register Full Event (RFDLF)
Bit 4/RFDL Abort Detect Event (RFDLAD)
Bit 5/BOC Clear Event (BOCC)
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
7
0
7
0
6
0
SR8
Status Register 8
24h
IMR8
Interrupt Mask Register 8
25h
6
0
BOCC
5
0
BOCC
5
0
RFDLAD
RFDLAD
4
0
4
0
116 of 237
RFDLF
RFDLF
3
0
3
0
TFDLE
TFDLE
2
0
2
0
RMTCH
RMTCH
1
0
1
0
RBOC
RBOC
0
0
0
0

Related parts for DS21Q55