DS2156L+ Maxim Integrated Products, DS2156L+ Datasheet - Page 7

• Manufacturer Part Number: DS2156L+
• Description: IC TXRX T1/E1/J1 1-CHIP 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2156L+

• Function: Single-Chip Transceiver
• Interface: E1, J1, T1, TDM, UTOPIA II
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

DS2156
Figure 34-13. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (Elastic Store Enabled)........... 240
Figure 34-14. Receive-Side Boundary Timing, RSYSCLK = 2.048MHz (Elastic Store Enabled)........... 240
Figure 34-15. Receive IBO Channel Interleave Mode Timing ................................................................ 241
Figure 34-16. Receive IBO Frame Interleave Mode Timing ................................................................... 242
Figure 34-17. G.802 Timing, E1 Mode Only ........................................................................................... 243
Figure 34-18. Transmit-Side Timing ....................................................................................................... 243
Figure 34-19. Transmit-Side Boundary Timing (Elastic Store Disabled) ................................................ 244
Figure 34-20. Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz (Elastic Store Enabled) ......... 244
Figure 34-21. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz (Elastic Store Enabled) .......... 245
Figure 34-22. Transmit IBO Channel Interleave Mode Timing ............................................................... 246
Figure 34-23. Transmit IBO Frame Interleave Mode Timing .................................................................. 247
Figure 36-1. Intel Bus Read Timing (BTS = 0/MUX = 1) ........................................................................ 251
Figure 36-2. Intel Bus Write Timing (BTS = 0/MUX = 1)......................................................................... 251
Figure 36-3. Motorola Bus Timing (BTS = 1/MUX = 1)........................................................................... 252
Figure 36-4. Intel Bus Read Timing (BTS = 0/MUX = 0) ........................................................................ 254
Figure 36-5. Intel Bus Write Timing (BTS = 0/MUX = 0)......................................................................... 254
Figure 36-6. Motorola Bus Read Timing (BTS = 1/MUX = 0) ................................................................. 255
Figure 36-7. Motorola Bus Write Timing (BTS = 1/MUX = 0) ................................................................. 255
Figure 36-8. Receive-Side Timing .......................................................................................................... 257
Figure 36-9. Receive-Side Timing, Elastic Store Enabled...................................................................... 258
Figure 36-10. Receive Line Interface Timing.......................................................................................... 258
Figure 36-11. Transmit-Side Timing ....................................................................................................... 260
Figure 36-12. Transmit-Side Timing, Elastic Store Enabled................................................................... 261
Figure 36-13. Transmit Line Interface Timing......................................................................................... 261
Figure 36-14. UTOPIA Interface Setup and Hold Times ........................................................................ 262
Figure 36-15. UTOPIA Interface Delay Times ........................................................................................ 262
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