DS2156L+ Maxim Integrated Products, DS2156L+ Datasheet - Page 43

• Manufacturer Part Number: DS2156L+
• Description: IC TXRX T1/E1/J1 1-CHIP 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2156L+

• Function: Single-Chip Transceiver
• Interface: E1, J1, T1, TDM, UTOPIA II
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

ADDRESS
xxh
DA
DD
BA
BD
CA
CD
DB
DC
BB
BC
BE
CB
CC
CE
DE
DF
B2
B3
B4
B5
B6
B7
B8
B9
BF
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
E0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Extend System Information Bus Register 1
Extend System Information Bus Register 2
Extend System Information Bus Register 3
Extend System Information Bus Register 4
In-Band Code Control Register
Transmit Code Definition Register 1
Transmit Code Definition Register 2
Receive Up Code Definition Register 1
Receive Up Code Definition Register 2
Receive Down Code Definition Register 1
Receive Down Code Definition Register 2
In-Band Receive Spare Control Register
Receive Spare Code Definition Register 1
Receive Spare Code Definition Register 2
Receive FDL Register
Transmit FDL Register
Receive FDL Match Register 1
Receive FDL Match Register 2
Interleave Bus Operation Control Register
Receive Align Frame Register
Receive Nonalign Frame Register
Receive Si Align Frame
Receive Si Nonalign Frame
Receive Remote Alarm Bits
Receive Sa4 Bits
Receive Sa5 Bits
Receive Sa6 Bits
Receive Sa7 Bits
Receive Sa8 Bits
Transmit Align Frame Register
Transmit Nonalign Frame Register
Transmit Si Align Frame
Transmit Si Nonalign Frame
Transmit Remote Alarm Bits
Transmit Sa4 Bits
Transmit Sa5 Bits
Transmit Sa6 Bits
Transmit Sa7 Bits
Transmit Sa8 Bits
Transmit Sa Bit Control Register
BERT Alternating Word Count Rate
BERT Repetitive Pattern Set Register 1
BERT Repetitive Pattern Set Register 2
BERT Repetitive Pattern Set Register 3
BERT Repetitive Pattern Set Register 4
BERT Control Register 1
REGISTER NAME
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SYMBOL
RDNCD1
RDNCD2
RFDLM1
RFDLM2
RUPCD1
RUPCD2
RSiNAF
TSiNAF
TSACR
RSCD1
RSCD2
BAWC
RSiAF
TSiAF
ESIB1
ESIB2
ESIB3
ESIB4
RNAF
TNAF
TCD1
TCD2
RSCC
RFDL
TFDL
IBOC
BRP1
BRP2
BRP3
BRP4
IBCC
RSa4
RSa5
RSa6
RSa7
RSa8
RRA
TSa4
TSa5
TSa6
TSa7
TSa8
TRA
RAF
TAF
BC1
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