DS2156L+ Maxim Integrated Products, DS2156L+ Datasheet - Page 176
DS2156L+
Manufacturer Part Number
DS2156L+
Description
IC TXRX T1/E1/J1 1-CHIP 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2156L.pdf
(265 pages)
Specifications of DS2156L+
Function
Single-Chip Transceiver
Interface
E1, J1, T1, TDM, UTOPIA II
Number Of Circuits
1
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
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24.5.3
The DS2156 can optionally insert a valid HEC byte in the cell header, or it can be programmed to
transparently transmit the HEC byte from ATM layer. When inserting a valid HEC byte, COSET (0x55)
addition can be optionally disabled. The generator polynomial used is 1 + X + X
idle/unassigned cell insertion (used for cell-rate decoupling), the DS2156 inserts a valid HEC byte with or
without COSET addition, depending on the TCRDS bit (U_TCR1.3). The DS2156 can optionally
scramble payload bytes, depending on the TPSE bit (U_TCR1.4) register bit. The polynomial used for
scrambling is X
HEC error in the cell header of cells transmitted in a controlled manner. If configured in HEC error-
insertion mode, it inserts HEC errors in HEC ON PERIOD number of cells and turns off HEC error
insertion for HEC OFF PERIOD number of cells set in the transmit HEC error-pattern register
(U_THEPR). This process repeats periodically, until HEC error insertion is disabled through U_TCR1.1.
Figure 24-6. Transmit Cell Flow
Transmit Processing
43
+ 1. For debugging purposes, the DS2156 can be configured to introduce a single-bit
Tx_Coset_enb
Tx_Crd_sel
HEC_OFF_period
Unassigned
Cell
HEC Insertion
ON
Cell
Idle
to Framer (PHY)
176 of 265
Scrambling
HEC Error
Cell Data
ON/OFF
Insertion
ON/OFF
Payload
HEC Insertion
Data Input
UTOPIA II
Transmit
ON/OFF
FIFO
Scrambling_enb
HEC_err_insert_enb
HEC_ON_period
HEC_insert_enb
Tx_Coset_enb
2
+ X
8
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