AM186CC-25KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-25KI\W C Datasheet - Page 92

• Manufacturer Part Number: AM186CC-25KI\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-25KI\W C

• Lead Free Status / Rohs Status: Not Compliant

Notes:
1. A pinstrap is used to enable or disable features based on the state of the pin during an external reset. The pinstrap must be
A-10
Signal Name
{ADEN}
{CLKSEL1}
{CLKSEL2}
{ONCE}
{UCSX8}
{USBSEL2}
{USBSEL1}
{USBXCVR}
held in its desired state for at least 4.5 clock cycles after the deassertion of RES. The pinstraps are sampled in an external
reset only (when RES is asserted), not during an internal watchdog timer-generated reset.
Multiplexed
Signal(s)
BHE
PIO34
HLDA
[PCS4]
PIO3
UCS
[MCS0]
PIO4
PCS1
PIO14
PCS0
PIO13
S0
Am186™CC Communications Controller Data Sheet
Table 31. Reset Configuration Pins (Pinstraps)
Description
Address Enable: If {ADEN} is held High or left floating during power-on reset, the
address portion of the AD bus (AD15–AD0) is enabled or disabled during LCS, UCS, or
other memory bus cycles based on how the software configures the
this case, the memory address is accessed on the A19–A0 pins. There is a weak
internal pullup resistor on {ADEN} so no external pullup is required. This mode of
operation reduces power consumption.
If {ADEN} is held Low on power-on reset, the AD bus drives both addresses and data,
regardless of how software configures the DA bit setting.
CPU PLL Mode Select 1 determines the PLL mode for the system clock source.
CPU PLL Mode Select 2 is sampled on the rising edge of reset and determines the PLL
mode for the system clock source. This pin has an internal pullup resistor that is active
only during reset. There are four CPU PLL modes that are selected by the values of
{CLKSEL1} and {CLKSEL2} as shown in Table 32. (For details on clocks see “Clock
Generation and Control” on page 40.)
ONCE Mode Request asserted Low places the Am186CC microcontroller into ONCE
mode. Otherwise, the controller operates normally. In ONCE mode, all pins are three-
stated and remain in that state until a subsequent reset occurs. To guarantee that the
controller does not inadvertently enter ONCE mode, {ONCE} has a weak internal pullup
resistor that is active only during a reset. A reset ending ONCE mode should be as long
as a power-on reset for the PLL to stabilize.
Upper Memory Chip Select, 8-Bit Bus asserted Low configures the upper chip select
region for an 8-bit bus size. This pin has a pullup resistor that is active only during reset,
so no external pullup is required to set the bus to 16-bit mode.
USB Clock Mode Selects 1–2 select the USB PLL operating mode. The pins have
internal pullups that are active only during reset. The USB PLL can operate in one of
three modes. With a crystal and the internal USB oscillator or an external oscillator, the
USB PLL can output 4x or 2x the input frequency. The USB PLL can also be disabled
and the USB peripheral controller can receive its clock from the CPU PLL, which is the
default mode. The pins are encoded as shown in Table 33. (For details on clocks see
“Clock Generation and Control” on page 40.)
USB External Transceiver Enable asserted Low disables the internal USB transceiver
and enables the pins needed to hook up an external transceiver. This pin has a pullup
resistor that is active only during reset, so no external pullup is required as long as the user
ensures that this input is not driven Low during a power-on reset.
{USBSEL1}
{CLKSEL1}
1
1
0
0
1
1
0
0
{USBSEL2}
{CLKSEL2}
Table 32. CPU PLL Modes
Table 33. USB PLL Modes
1
0
1
0
1
0
1
0
USB PLL Mode
Use system clock (after CPU PLL mode
select), USB PLL disabled (default)
4x, USB PLL enabled
2x, USB PLL enabled
Reserved
CPU PLL Mode
2X, CPU PLL enabled (default)
4X, CPU PLL enabled
1X, CPU PLL enabled
PLL Bypass
1
DA bit setting
. In