AM186CC-25KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-25KI\W C Datasheet - Page 18

• Manufacturer Part Number: AM186CC-25KI\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-25KI\W C

• Lead Free Status / Rohs Status: Not Compliant

18
Signal Name
RES
RESOUT
[UCLK]
USBX1
USBX2
X1
X2
PINSTRAPS (See Table 31, “Reset Configuration Pins (Pinstraps),” on page A-10.)
RESERVED
RSVD_101
RSVD_102
RSVD_103
RSVD_104
Multiplexed
Signal(s)
—
—
[USBSOF]
[USBSCI]
PIO21
—
—
—
—
UTXDPLS
UTXDMNS
UXVOE
UXVRCV
Am186™CC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Type Description
STI
STI
STI
STI
—
—
—
—
O
O
O
Reset requires the Am186CC controller to perform a reset. When RES is
asserted, the controller immediately terminates its present activity, clears its
internal logic, and on the deassertion of RES, transfers CPU control to the reset
address FFFF0h.
RES must be asserted for at least 1 ms to allow the internal circuits to stabilize.
RES can be asserted asynchronously to CLKOUT because RES is synchronized
internally. For proper initialization, V
CLKOUT must be stable for more than four CLKOUT periods during which RES
is asserted.
If RES is asserted while the watchdog timer is performing a watchdog-timer reset,
the external reset takes precedence over the watchdog-timer reset. This means
that the RESOUT signal asserts as with any external reset and the WDTCON
register will not have the RSTFLAG bit set. In addition, the controller will exit reset
based on the external reset timing, i.e., 4.5 clocks after the deassertion of RES
rather than 2
The Am186CC controller begins fetching instructions approximately 6.5
CLKOUT periods after RES is deasserted. This input is provided with a Schmitt
trigger to facilitate power-on RES generation via an RC network.
Reset Out indicates that the Am186CC
externally or internally), and the signal can be used as a system reset to reset
any external peripherals connected to RESOUT.
During an external reset, RESOUT remains active (High) for two clocks after
RES is deasserted. The controller exits reset and begins the first valid bus cycle
approximately 4.5 clocks after RES is deasserted.
UART Clock can be used instead of the processor clock as the source clock for
either the UART or the High-Speed UART. The source clock for the UART and
the High-Speed UART are selected independently and both can use the same
source.
USB Controller Crystal Input (USBX1) and USB Controller Crystal Output
(USBX2) provide connections for a fundamental mode, parallel-resonant crystal
used by the internal USB oscillator circuit.
If the CPU crystal is used to generate the USB clock, USBX1 must be pulled down.
CPU Crystal Input (X1) and CPU Crystal Output (X2) provide connections for
a fundamental mode, parallel-resonant crystal used by the internal oscillator
circuit. If an external oscillator is used, inject the signal directly into X1 and leave
X2 floating.
RSVD_101–RSVD_104 are reserved unless pinstrap {USBXCVR} is sampled
Low on the rising edge of RESET. When reserved, these pins should not be
connected.
16
clocks after the watchdog timer timeout occurred.
CC
must be within specifications, and
controller
is being reset (either