AM186CC-25KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-25KI\W C Datasheet - Page 17

• Manufacturer Part Number: AM186CC-25KI\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-25KI\W C

• Lead Free Status / Rohs Status: Not Compliant

Signal Name
S2
S1
S0
WHB
WLB
WR
CLOCKS/RESET/WATCHDOG TIMER
CLKOUT
Multiplexed
Signal(s)
—
—
{USBXCVR}
—
—
[PIO15]
—
Am186™CC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Type Description
O
O
O
O
O
Bus Cycle Status 2–0 indicate to the system the type of bus cycle in progress.
S2 can be used as a logical memory or I/O indicator, and S1 can be used as a
data transmit or receive indicator. S2–S0 are three-stated during bus hold and
three-stated with a pullup during reset. The S2–S0 pins are encoded as follows:
Write High Byte and Write Low Byte indicate to the system which bytes of the
data bus (upper, lower, or both) participate in a write cycle. In 80C186
microcontroller designs, this information is provided by BHE, AD0, and WR.
However, by using WHB and WLB, the standard system interface logic and
external address latch that were required are eliminated.
WHB is asserted with AD15–AD8. WHB is the logical AND of BHE and WR. This
pin is three-stated with a pullup during bus-hold or reset conditions.
WLB is asserted with AD7–AD0. WLB is the logical AND of AD0 and WR. This
pin is three-stated with a pullup during bus-hold or reset conditions.
Write Strobe indicates to the system that the data on the bus is to be written to
a memory or I/O device. WR is three-stated with a pullup during bus-hold or reset
conditions.
Clock Output supplies the clock to the system. Depending on the values of the
CPU mode select pinstraps, {CLKSEL1} and {CLKSEL2}, CLKOUT operates at
either the PLL frequency or the source input frequency during PLL Bypass
mode. (See Table 31, “Reset Configuration Pins (Pinstraps),” on page A-10.)
CLKOUT remains active during bus-hold or reset conditions.
The DISCLK bit in the SYSCON register can be set to disable the CLKOUT
signal. Refer to the Am186™CC/CH/CU Microcontrollers Register Set Manual
(order #21916).
All synchronous AC timing specifications not associated with SSI, HDLCs,
UARTs, and the USB are synchronous to CLKOUT.
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Bus Status Pins
Bus Cycle
Reserved
Read data from I/O
Write data to I/O
Halt
Instruction fetch
Read data from memory
Write data to memory
None (passive)
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