AM186CC-25KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-25KI\W C Datasheet - Page 26

• Manufacturer Part Number: AM186CC-25KI\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-25KI\W C

• Lead Free Status / Rohs Status: Not Compliant

26
Signal Name
[PCM_FSC_C]
[PCM_TSC_C]
HDLC Channel D (PCM)
[PCM_RXD_D]
[PCM_TXD_D]
[PCM_CLK_D]
[PCM_FSC_D]
[PCM_TSC_D]
HDLC Channel A (GCI)
[GCI_DD_A]
[GCI_DU_A]
[GCI_DCL_A]
[GCI_FSC_A]
UNIVERSAL SERIAL BUS
[UDMNS]
[UDPLS]
USBD+
USBD–
Multiplexed
Signal(s)
[DCE_TCLK_C]
PIO23
[DCE_CTS_C]
PIO44
[RXD_U] (UART)
DCE_RXD_D
PIO26
[TXD_U] (UART)
[DCE_TXD_D]
PIO20
[RTR_U] (UART)
DCE_RCLK_D
PIO25
[CTS_U] (UART)
[DCE_TCLK_D]
PIO24
[CTS_HU] (High-
Speed UART)
[DCE_CTS_D]
PIO46
DCE_RXD_A
[PCM_RXD_A]
DCE_TXD_A
[PCM_TXD_A]
DCE_RCLK_A
[PCM_CLK_A]
DCE_TCLK_A
[PCM_FSC_A]
USBD–
USBD+
[UDPLS]
[UDMNS]
Am186™CC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Type Description
O-LS-
OD
STI
STI
STI
OD
OD
OD
STI
STI
STI
STI
OD
B-
B-
B
B
B
PCM Frame Synchronization Clock: For PCM Highway operation,
[PCM_FSC_C] provides the Frame Synchronization Clock input (usually 8 kHz)
for the channel C PCM Highway interface. [PCM_FSC_C] becomes a frame
synchronization source output when the GCI to PCM Highway clock and frame
synchronization conversion are enabled.
PCM Time Slot Control C enables an external buffer device when channel C
PCM Highway data is present on the [PCM_TXD_C] output pin in PCM Highway
mode.
PCM Receive Data Channel D is the serial data input pin for the channel D PCM
Highway interface.
PCM Transmit Data Channel D is the serial data output pin for the channel D
PCM Highway interface.
PCM Clock is the single transmit and receive data clock pin for the channel D
PCM Highway interface.
PCM Frame Synchronization Clock provides the Frame Synchronization Clock
input (usually 8 kHz) for the channel D PCM Highway interface.
PCM Time Slot Control D enables an external buffer device when channel D
PCM Highway data is present on the [PCM_TXD_D] output pin in PCM Highway
mode.
GCI Data Downstream is the serial data input pin for the channel A GCI
interface.
GCI Data Upstream is the serial data output pin for the channel A GCI interface.
GCI Data Clock is the single transmit and receive channel A GCI data clock input
generated by an upstream device. The data clock frequency must be twice the data rate.
GCI Frame Synchronization Clock provides the 8-kHz Frame Synchronization
Clock input for the channel A GCI interface generated by an upstream device.
USB External Transceiver Gated Differential Plus and USB External
Transceiver Gated Differential Minus are inputs from the external USB
transceiver used to detect single-ended zero and error conditions. The signals
have the following meanings:
USB Differential Plus and USB Differential Minus form the bidirectional
electrical data interface for the USB port. The pins form a differential pair that
can be connected to a physical USB connector without an external transceiver.
UDPLS
0
0
1
1
USB External Transceiver Signals
UDMNS
0
1
0
1
Status
Single-Ended Zero (SE0)
Full speed
Reserved
Error