AM186CC-25KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-25KI\W C Datasheet - Page 31

• Manufacturer Part Number: AM186CC-25KI\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-25KI\W C

• Lead Free Status / Rohs Status: Not Compliant

Four HDLC Channels and Four TSAs
The Am186CC microcontroller provides four HDLC
channels that support the HDLC, SDLC, LAP-B, LAP-D,
PPP, and v.120 protocols. The HDLC channels can also
be used in transparent mode to support v.110. Each
HDLC channel can connect to an external serial
interface directly (nonmultiplexed mode), or can pass
through a TSA (multiplexed mode). The flexible interface
multiplexing arrangement allows each HDLC channel to
have its own external raw DCE or PCM highway
interface, share the GCI interface with up to two other
channels, share a common PCM highway or other time
TDM bus with three or more channels, or work in some
combination.
Each HDLC channel’s independent TSA allows it to
extract a subset of data from a TDM bus. The entire
frame, or as little as 1 bit per frame, can be extracted.
Twelve-bit counters define the start/stop bit times as
the number of bits after frame synchronization. The
time slot can be an arbitrary number of bits up to 4096
bits. Start bit and stop bit times identify the isolated
portion of the TDM frame. Support of less than eight
bits per time slot, or bit slotting , allows isolation of from
one to eight bits in a single time slot, providing a
convenient way to work with D-channel data. Each
TDM bus can have up to 512 8-bit time slots. Support
of these features allows interoperation with PCM
highway, E1, IOM-2, T1, and other TDM buses.
The HDLC channels have features that make the
Am186CC microcontroller an attractive device for use
where general HDLC capability is required. These
features include CTS/RTR hardware handshaking and
auto-enable operation, collision detection for multidrop
applications, transparency mode, address comparison
on receive, flag or mark idle operation, two dedicated
buffer descriptor ring SmartDMA channels per HDLC,
transmit and receive FIFOs, and full-duplex data
transfer. Each TSA channel can support a burst data
rate to/from the HDLC of up to 10 Mbit/s in both raw
DCE and PCM Highway modes, and up to 768 Kbit/s in
GCI mode. Total system data throughput is highly
dependent on the amount of per-packet and per-byte
CPU processing, the rate at which packets are being
sent, and other CPU activity.
When combined with the TSAs, the HDLC channels
can be used in a wide variety of applications such as
ISDN basic rate interface (BRI) and primary rate
interface (PRI) B and D channels, PCM highway, X.25,
Frame Relay, and other proprietary Wide Area Network
(WAN) connections.
General Circuit Interface
The General Circuit Interface (GCI) is an interface
specification developed jointly by Alcatel, Italtel, GPT,
and Siemens. This specification defines an industry-
Am186™CC Communications Controller Data Sheet
s t a n d a r d
telecommunications integrated circuits. The standard
covers linecard, NT1, and terminal architectures for
ISDN applications. The Am186CC microcontroller
supports the terminal version of GCI.
The Am186CC GCI interface provides a glueless
connection between the Am186CC microcontroller and
GCI/IOM-2 based ISDN transceiver devices, such as
the AMD Am79C30 or Am79C32. The Am186CC
microcontroller GCI interface provides a 4-pin
connection to the transceiver device. The Am186CC
microcontroller also allows conversion of the GCI clock
and frame synchronization into a format usable by
PCM codecs, allowing PCM codecs to be used directly
with GCI/IOM-2 transceivers. Additional GCI features
include slave mode with pin reversal, Terminal Interchip
Communication (TIC) bus support for D channel
arbitration and collision detection, and support for one
Monitor and two Command/Indicate channels.
Eight SmartDMA™ Channels
The Am186CC microcontroller provides a total of 12
DMA channels. Eight of these channels are SmartDMA
channels, which provide a method for transmission and
reception of data across multiple memory buffers and a
sophisticated buffer-chaining mechanism. These
channels are always used in pairs: transmitter and
receiver. The transmit channels can only transfer data
from memory to a peripheral; the receive channels can
only transfer data from a peripheral to memory.
Four of the channels (two pairs) are dedicated for use
with two of the on-board HDLC channels. The
remaining four SmartDMA channels (two pairs) can
support either the third or fourth HDLC channel or USB
endpoints A, B, C, or D.
In addition to the eight SmartDMA channels, the
Am186CC microcontroller provides four general-
purpose DMA channels. For more information about
the four general-purpose DMA channels, refer to “Four
General-Purpose DMA Channels” on page 32.
Two Asynchronous Serial Ports
The Am186CC microcontroller has two asynchronous
serial ports (a UART and a High-Speed UART) that
provide full-duplex, bidirectional data transfer at
speeds of up to 115.2 Kbit/s or up to 460 Kbit/s,
respectively. The High-Speed UART has 16-byte
transmit and 32-byte receive FIFOs, special-character
matching, and automatic baud-rate detection, which is
suitable for implementation of a Hayes-compatible
modem interface to a host PC. A lower speed UART is
also available that is typically used for a low baud-rate
system configuration port or debug port. Each of these
UARTs can derive its baud rate from the system clock
or from a separate baud-rate generator clock input.
Both UARTs support 7-, 8-, or 9-bit data transfers;
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