AM186CC-25KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-25KI\W C Datasheet - Page 43

• Manufacturer Part Number: AM186CC-25KI\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-25KI\W C

• Lead Free Status / Rohs Status: Not Compliant

External Clock Source
The internal oscillator also can be driven by an external
clock source. The external clock source should be
connected to the input of the inverting amplifier (X1 or
U S B X 1 ) w i t h t h e o u t p u t ( X 2 o r U S B X 2 ) l e f t
unconnected. Figure 11 shows the system clocks
using an external clock source (oscillator bypass).
Note: X1, X2, USBX1, and USBX2 are not 5-V toler-
ant and have a maximum input equal to V
Figure 11. External Interface to Support Clocks—
Static Operation
The Am186CC controller is a fully static design and can
be placed in static mode by stopping the input clock.
PLL bypass mode must be used with an external clock
source. For PLL bypass mode, refer to the PLL Bypass
Mode discussion below.
Note: It is the responsibility of the system designer to
ensure that no short clock phases are generated when
starting or stopping the clock.
PLL Bypass Mode
The Am 186CC microcontroller provides a PLL Bypass
mode that allows the X1 input frequency to be
anywhere from 0 to 24 MHz. When the microcontroller
is in PLL Bypass mode, the CLKOUT frequency equals
the X1 input frequency. This mode must be used with
an external clock source. For PLL Bypass mode
enabling, refer to Table 31, “Reset Configuration Pins
(Pinstraps),” on page A-10.
UART/High-Speed UART
System Clock
External
Clock
Clock Select
UCLK
External Clock Source
NC
X1/USBX1
X2/USBX2
Am186™CC Communications Controller Data Sheet
Figure 12. UART and High-Speed UART Clocks
CC
Autobaud Clock
(High-Speed UART Only)
.
Divisor
Baud
Oversample
When changing frequency in PLL Bypass mode, the X1
input must not have any short or “runt” pulses. At
24 MHz, the nominal High/Low time is 21 ns. The
actual High times and Low times must not fall below 16
ns. These values allow a 60%/40% duty cycle at X1.
In the Am186CC microcontroller, the system clock
must be at the same or a greater frequency than the
HDLC clock and UCLK (if using UCLK). Therefore, if
reducing the system clock frequency, disable these
interfaces or run them at a lower frequency.
The USB PLL and USBX1 determine the USB clock.
USB requires the system clock to be 24 MHz or greater.
Therefore, disable the USB peripheral controller before
slowing the system clock to less than 24 MHz. If USB
is not used, the USBX1 can be pulled down.
UART Baud Clock
The UARTs (low- and high-speed) have two possible
clock sources: the system clock or the UCLK input pin.
If UCLK is used for the UART clock, the system clock
must be at least the same frequency as UCLK. The
clock configurations are shown graphically in
Figure 12.
The baud clock is generated by dividing the clock
source by the value of baud rate divisor register. The
serial port logic can select its baud rate clock from
either an external pin (UCLK) or from the system clock.
The system or UCLK clock is selected independent of
any other settings.
The formula for determining the baud rate divisor
register value is:
BAUDDIV = (clock frequency/(16 • baud rate))
Note: UCLK cannot be clocked at a frequency higher
than the system cock frequency.
Clock
Oversampling
Divide for
Baud Clock
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