AM186CC-25KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-25KI\W C Datasheet - Page 16

• Manufacturer Part Number: AM186CC-25KI\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-25KI\W C

• Lead Free Status / Rohs Status: Not Compliant

16
Signal Name
HLDA
HOLD
RD
S6
SRDY
Multiplexed
Signal(s)
{CLKSEL1}
—
—
—
[PIO35]
Am186™CC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Type Description
STI
STI
O
O
O
Bus-Hold Acknowledge is asserted to indicate to an external bus master that
the Am186CC controller has relinquished control of the local bus. When an
external bus master requests control of the local bus (by asserting HOLD), the
microcontroller completes the bus cycle in progress, then relinquishes control of
the bus to the external bus master by asserting HLDA and three-stating S2–S0,
AD15–AD0, S6, and A19–A0. The following are also three-stated and have
pullups: UCS, LCS, MCS3–MCS0, PCS7–PCS0, DEN, RD, WR, BHE, WHB,
WLB, and DT/R. ALE is three-stated and has a pulldown.
When the external bus master has finished using the local bus, it indicates this
to the Am186CC controller by deasserting HOLD. The controller responds by
deasserting HLDA.
If the Am186CC controller requires access to the bus (for example, for refresh),
the controller deasserts HLDA before the external bus master deasserts HOLD.
The external bus master must be able to deassert HOLD and allow the controller
access to the bus. See the timing diagrams for bus hold on page 70.
Bus-Hold Request indicates to the Am186CC controller that an external bus
master needs control of the local bus.
The Am186CC controller’s HOLD latency time—the time between HOLD
request and HOLD acknowledge—is a function of the activity occurring in the
processor when the HOLD request is received. A HOLD request is second only
to DRAM refresh requests in priority of activity requests received by the
processor. This implies that if a HOLD request is received just as a DMA transfer
begins, the HOLD latency can be as great as four bus cycles. This occurs if a
DMA word transfer operation is taking place from an odd address to an odd
address. This is a total of 16 clock cycles or more if wait states are required. In
addition, if locked transfers are performed, the HOLD latency time is increased
by the length of the locked transfer. HOLD latency is also potentially increased
by DRAM refreshes.
The board designer is responsible for properly terminating the HOLD input.
For more information, see the HLDA pin description.
Read Strobe indicates to the system that the Am186CC controller is performing
a memory or I/O read cycle. RD is guaranteed to not be asserted before the
address and data bus is three-stated during the address-to-data transition. RD
is three-stated with a pullup during bus-hold or reset conditions.
Bus Cycle Status Bit 6: This signal is asserted during t
initiated bus cycle or a refresh cycle. S6 is three-stated during bus hold and
three-stated with a pulldown during reset.
Synchronous Ready indicates to the Am186CC controller that the addressed
memory space or I/O device will complete a data transfer. The SRDY pin accepts
an active High input synchronized to CLKOUT.
Using SRDY instead of ARDY allows a relaxed system timing because of the
elimination of the one-half clock period required to internally synchronize ARDY.
To always assert the ready condition to the microcontroller, tie SRDY High. If the
system does not use SRDY, tie the pin Low to yield control to ARDY.
1
–t
4
to indicate a DMA-