PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 47

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.68 CAPABILITY ID REGISTER – OFFSET A8h
6.3.69 NEXT POINTER REGISTER – OFFSET A8h
Pericom Semiconductor - Confidential
BIT
3:2
5:4
7:6
8
9
10
11
12
13
14
15
16
18:17
31:19
BIT
7:0
BIT
FUNCTION
S_CLKOUT1 Enable
S_CLKOUT2 Enable
S_CLKOUT3 Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Secondary Clock Stop Status
Secondary Clkrun Protocol
Enable
Clkrun Mode
ASPM L0s enable control
Scrambling control
Reserved
FUNCTION
Capability ID
FUNCTION
TYPE
TYPE
TYPE
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
Page 47 of 78
DESCRIPTION
S_CLKOUT (Slot 1) Enable for forward bridge mode only
00: enable S_CLKOUT1
01: enable S_CLKOUT1
10: enable S_CLKOUT1
11: disable S_CLKOUT1 and driven LOW
Reset to 00
S_CLKOUT (Slot 2) Enable for forward bridge mode only
00: enable S_CLKOUT2
01: enable S_CLKOUT2
10: enable S_CLKOUT2
11: disable S_CLKOUT2 and driven LOW
Reset to 00
S_CLKOUT (Slot 3) Enable for forward bridge mode only
00: enable S_CLKOUT3
01: enable S_CLKOUT3
10: enable S_CLKOUT3
11: disable S_CLKOUT3 and driven LOW
Reset to 00
Reset to 0h
Reset to 0h
Reset to 0h
Reset to 0h
Reset to 0h
Secondary clock stop status
0: secondary clock not stopped
1: secondary clock stopped
Reset to 0
0: disable protocol
1: enable protocol
Reset to 0
0: Stop the secondary clock only when bridge is at D3hot state
1: Stop the secondary clock whenever the secondary bus is idle and there are
no requests from the primary bus
Reset to 0
0: bridge may enter ASPM L0s regardless if Receiver is Electrical Idle
1: bridge may enter ASPM L0s only if Receiver is Electrical Idle
Reset to 1
Reset to 0
Reset to 0
DESCRIPTION
Capability ID for subsystem ID and subsystem vendor ID
Reset to 0Dh
DESCRIPTION
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL