PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 28

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.7
6.3.8
6.3.9
6.3.10 RESERVED REGISTERS – OFFSET 10h TO 17h
6.3.11 PRIMARY BUS NUMBER REGISTER – OFFSET 18h
6.3.12 SECONDARY BUS NUMBER REGISTER – OFFSET 18h
6.3.13 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h
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CACHE LINE SIZE REGISTER – OFFSET 0Ch
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
PRIMARY HEADER TYPE REGISTER – OFFSET 0Ch
BIT
1:0
2
3
4
5
7:6
BIT
15:8
BIT
22:16
23
31:24
BIT
7:0
BIT
15:8
BIT
FUNCTION
Reserved
Cache Line Size
Cache Line Size
Cache Line Size
Cache Line Size
Reserved
FUNCTION
Primary Latency Timer
FUNCTION
PCI-to-PCI bridge
configuration
Single Function Device
Reserved
FUNCTION
Primary Bus Number
FUNCTION
Secondary Bus Number
FUNCTION
TYPE
TYPE
TYPE
TYPE
TYPE
TYPE
RO /
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Bit [1:0] not supported
Reset to 00
1: Cache line size = 4 double words
Reset to 0
1: Cache line size = 8 double words
Reset to 0
1: Cache line size = 16 double words
Reset to 0
1: Cache line size = 32 double words
Reset to 0
Bit [7:6] not supported
Reset to 00
DESCRIPTION
8 bits of primary latency timer in PCI bus
FORWARD BRIDGE – RO with reset to 00h
REVERSE BRIDGE – RW with reset to 00h in PCI mode
DESCRIPTION
PCI-to-PCI bridge configuration (10 – 3Fh)
Reset to 0000001
0: Indicates single function device
Reset to 0
Reset to 00h
DESCRIPTION
Reset to 00h
DESCRIPTION
Reset to 00h
DESCRIPTION
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL