PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 37

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.33 RESERVED REGISTER – OFFSET 44h
6.3.34 ARBITER ENABLE REGISTER – OFFSET 48h
6.3.35 ARBITER MODE REGISTER – OFFSET 48h
Pericom Semiconductor - Confidential
BIT
31:0
BIT
0
1
2
3
4
5
6
7
8
BIT
9
10
11
19:12
FUNCTION
Reserved
FUNCTION
Enable Arbiter 0
Enable Arbiter 1
Enable Arbiter 2
Enable Arbiter 3
Reserved
Reserved
Reserved
Reserved
Reserved
FUNCTION
External Arbiter Bit
Broken Master Timeout
Enable
Broken Master Refresh
Enable
Arbiter Fairness Counter
TYPE
TYPE
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
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DESCRIPTION
Reset to 00000000h
DESCRIPTION
0: Disable arbitration for internal PI7C9X111SL request
1: Enable arbitration for internal PI7C9X111SL request
Reset to 1
0: Disable arbitration for master 1
1: Enable arbitration for master 1
Reset to 1
0: Disable arbitration for master 2
1: Enable arbitration for master 2
Reset to 1
0: Disable arbitration for master 3
1: Enable arbitration for master 3
Reset to 1
Reset to 1
Reset to 0
Reset to 0
Reset to 0
Reset to 0
DESCRIPTION
=0: Enable internal arbiter
=1: When using an external arbiter
Reset to 0
0: Broken master timeout disable
1: This bit enables the internal arbiter to count 16 PCI bus cycles while
waiting for FRAME_L to become active when a device’s PCI bus GNT is
active and the PCI bus is idle. If the broken master timeout expires, the PCI
bus GNT for the device is de-asserted.
Reset to 0
0: A broken master will be ignored forever after de-asserting its REQ_L for
at least 1 clock
1: Refresh broken master state after all the other masters have been served
once
Reset to 0
08h: These bits are the initialization value of a counter used by the internal
arbiter. It controls the number of PCI bus cycles that the arbiter holds a
device’s PCI bus GNT active after detecting a PCI bus REQ_L from another
device. The counter is reloaded whenever a new PCI bus GNT is asserted.
For every new PCI bus GNT, the counter is armed to decrement when it
detects the new fall of FRAME_L. If the arbiter fairness counter is set to 00h,
the arbiter will not remove a device’s PCI bus GNT until the device has de-
asserted its PCI bus REQ.
Reset to 08h
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL