PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 25

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3
6.3.1
6.3.2
6.3.3
The following section describes the configuration space when the device is in transparent mode. The descriptions
for different register type are listed as follow:
Pericom Semiconductor - Confidential
PCI CONFIGURATION REGISTERS
VENDOR ID – OFFSET 00h
DEVICE ID – OFFSET 00h
COMMAND REGISTER – OFFSET 04h
Register Type
RO
ROS
RW
RWC
RWS
RWCS
BIT
15:0
BIT
31:16
BIT
0
1
2
3
4
5
FUNCTION
Vendor ID
FUNCTION
Device ID
FUNCTION
I/O Space Enable
Memory Space Enable
Bus Master Enable
Special Cycle Enable
Memory Write and
Invalidate Enable
VGA Palette Snoop Enable
TYPE
TYPE
TYPE
RO /
RW
RW
RW
RW
RO
RO
RO
RO
Descriptions
Read Only
Read Only and Sticky
Read/Write
Read/Write “1” to clear
Read/Write and Sticky
Read/Write “1” to clear and Sticky
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DESCRIPTION
Identifies Pericom as the vendor of this device. Returns 12D8h when read.
DESCRIPTION
Identifies this device as the PI7C9X111SL. Returns E111 when read.
DESCRIPTION
0: Ignore I/O transactions on the primary interface
1: Enable response to memory transactions on the primary interface
Reset to 0
0: Ignore memory read transactions on the primary interface
1: Enable memory read transactions on the primary interface
Reset to 0
0: Do not initiate memory or I/O transactions on the primary interface and
disable response to memory and I/O transactions on the secondary interface
1: Enable the bridge to operate as a master on the primary interfaces for
memory and I/O transactions forwarded from the secondary interface.
Reset to 0
0: PI7C9X111SL does not respond as a target to Special Cycle transactions,
so this bit is defined as Read-Only and must return 0 when read
Reset to 0
0: PI7C9X111SL does not originate a Memory Write and Invalidate
transaction. Implements this bit as Read-Only and returns 0 when read
(unless forwarding a transaction for another master).
Reset to 0
This bit applies to reverse bridge only.
0: Ignore VGA palette access on the primary
1: Enable positive decoding response to VGA palette writes on the primary
interface with I/O address bits AD [9:0] equal to 3C6h, 3C8h, and 3C9h
(inclusive of ISA alias; AD [15:0] are not decoded and may be any value)
Reset to 0
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL