PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 36

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

Pericom Semiconductor - Confidential
BIT
16
18:17
19
20
22:21
23
25:24
26
29:27
30
31
FUNCTION
PCI Retry Counter Status
PCI Retry Counter Control
PCI Discard Timer Disable
PCI Discard Timer Short
Duration
Configuration Request Retry
Timer Counter Value
Control
Delayed Transaction Order
Control
Completion Timer Counter
Value Control
Isochronous Traffic Support
Enable
Traffic Class Used For
Isochronous Traffic
Power Saving mode enable
Primary Configuration
Access Lockout
TYPE
RWC
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Page 36 of 78
DESCRIPTION
0: The PCI retry counter has not expired since the last reset
1: The PCI retry counter has expired since the last reset
Reset to 0
00: No expiration limit
01: Allow 256 retries before expiration
10: Allow 64K retries before expiration
11: Allow 2G retries before expiration
Reset to 00
0: Enable the PCI discard timer in conjunction with bit [27] offset 3Ch
(bridge control register)
1: Disable the PCI discard timer in conjunction with bit [27] offset 3Ch
(bridge control register)
Reset to 0
0: Use bit [24] offset 3Ch for forward bridge or bit [25] offset 3Ch for
reverse bridge to indicate how many PCI clocks should be allowed before the
PCI discard timer expires
1: 64 PCI clocks allowed before the PCI discard timer expires
Reset to 0
00: Timer expires at 25us
01: Timer expires at 0.5ms
10: Timer expires at 5ms
11: Timer expires at 25ms
Reset to 01
0: Enable out-of-order capability between delayed transactions
1: Disable out-of-order capability between delayed transactions
Reset to 0
00: Timer expires at 50us
01: Timer expires at 10ms
10: Timer expires at 50ms
11: Timer disabled
Reset to 01
0: All memory transactions from PCI to PCIe will be mapped to TC0
1: All memory transactions from PCI to PCIe will be mapped to Traffic Class
defined in bit [29:27] of offset 40h.
Reset to 0
Reset to 001
=0 : disable the power saving mode;
=1 : enable the power saving mode, and the internal clock for mac/dll/tlp
=0 : 9X111 configuration space can be accessed from both interface.
=1 : 9X111 configuration space can only be accessed from the
and pci logic is disabled at L1s and L1 state.
secondary interface. primary bus accessed receives completion
with CRS status for forward bridge, or target retry for
reverse bridge.
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL