PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 26

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.4
Pericom Semiconductor - Confidential
PRIMARY STATUS REGISTER – OFFSET 04h
BIT
6
7
8
9
10
15:11
BIT
18:16
19
20
21
22
23
24
FUNCTION
Parity Error Response
Enable
Wait Cycle Control
SERR_L Enable Bit
Fast Back-to-Back Enable
Interrupt Disable
Reserved
FUNCTION
Reserved
Reserved
Capability List Capable
66MHz Capable
Reserved
Fast Back-to-Back Capable
Master Data Parity Error
Detected
RO
RO
RO
RWC
TYPE
TYPE
RW
RW
RW
RO
RO
RO
RO
RO
RO
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DESCRIPTION
0: May ignore any parity error that is detected and take its normal action
1: This bit if set, enables the setting of Master Data Parity Error bit in the
Status Register when poisoned TLP received or parity error is detected and
takes its normal action
Reset to 0
Wait cycle control not supported
Reset to 0
0: Disable
1: Enable PI7C9X111SL in forward bridge mode to report non-fatal or fatal
error message to the Root Complex. Also, in reverse bridge mode to assert
SERR_L on the primary interface
Reset to 0
Fast back-to-back enable not supported
Reset to 0
This bit applies to reverse bridge only.
0: INTA_L can be asserted on PCI interface
1: Prevent INTA_L from being asserted on PCI interface
Reset to 0
Reset to 00000
DESCRIPTION
Reset to 000
Reset to 0
1: PI7C9X111SL supports the capability list (offset 34h in the pointer to the
data structure)
Reset to 1
This bit applies to reverse bridge only.
1: 66MHz capable
Reset to 0 when forward bridge or 1 when reverse bridge.
Reset to 0
This bit applies to reverse bridge only.
1: Enable fast back-to-back transactions
Reset to 0 when forward bridge or 1 when reverse bridge in PCI mode.
Bit set if its Parity Error Enable bit is set and either of the conditions occurs
on the primary:
FORWARD BRIDGE –
Receives a completion marked poisoned
Poisons a write request
REVERSE BRIDGE –
Detected parity error when receiving data or Split Response for read
Observes P_PERR_L asserted when sending data or receiving Split Response
for write
Receives a Split Completion Message indicating data parity error occurred
for non-posted write
Reset to 0
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL