ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 9

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

Preliminary Technical Data
SERIAL PORTS (SPORTS)
The ADSP-BF561 incorporates two dual-channel synchronous
serial ports (SPORT0 and SPORT1) for serial and multiproces-
sor communications. The SPORTs support the following
features:
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The ADSP-BF561 has one SPI-compatible ports that enable the
processor to communicate with multiple SPI-compatible
devices.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSIx, and Master Input-
Slave Output, MISO) and a clock pin (Serial Clock, SCK). One
SPI chip select input pin (SPISS) let other SPI devices select the
DSP, and seven SPI chip select output pins (SPISEL7–1) let the
DSP select other SPI devices. The SPI select pins are reconfig-
ured Programmable Flag pins. Using these pins, the SPI ports
• I
• Bidirectional operation – Each SPORT has two sets of inde-
• Buffered (8-deep) transmit and receive ports – Each port
• Clocking – Each transmit and receive port can either use an
• Word length – Each SPORT supports serial data words
• Framing – Each transmit and receive port can run with or
• Companding in hardware – Each SPORT can perform
• DMA operations with single-cycle overhead – Each SPORT
• Interrupts – Each transmit and receive port generates an
• Multichannel capability – Each SPORT supports 128 chan-
pendent transmit and receive pins, enabling eight channels
of I
has a data register for transferring data words to and from
other DSP components and shift registers for shifting data
in and out of the data registers.
external serial clock or generate its own, in frequencies
ranging from (f
from 3 to 32 bits in length, transferred most-significant-bit
first or least-significant-bit first.
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulsewidths and early or late
frame sync.
A-law or µ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
can automatically receive and transmit multiple buffers of
memory data. The DSP can link or chain sequences of
DMA transfers between a SPORT and memory.
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
2
S capable operation.
2
S stereo audio.
SCLK
/131,070) Hz to (f
SCLK
/2) Hz.
Rev. PrC | Page 9 of 52 | April 2004
provide a full duplex, synchronous serial interface, which sup-
ports both master and slave modes and multimaster
environments.
Each SPI port’s baud rate and clock phase/polarities are pro-
grammable (see SPI Clock Rate equation), and each has an
integrated DMA controller, configurable to support transmit or
receive data streams. The SPI’s DMA controller can only service
unidirectional accesses at any given time.
During transfers, the SPI ports simultaneously transmit and
receive by serially shifting data in and out on their two serial
data lines. The serial clock line synchronizes the shifting and
sampling of data on the two serial data lines.
UART PORT
The ADSP-BF561 provides a full duplex Universal Asynchro-
nous Receiver/Transmitter (UART) ports (UART0 and
UART1) fully compatible with PC-standard UARTs. The UART
ports provide a simplified UART interface to other peripherals
or hosts, supporting full duplex, DMA supported, asynchronous
transfers of serial data. Each UART port includes support for 5
to 8 data bits; 1 or 2 stop bits; and none, even, or odd parity. The
UART ports support two modes of operation, as follows:
Each UART port’s baud rate (see UART Clock Rate equation),
serial data format, error code generation and status, and inter-
rupts are programmable. In the UART Clock Rate equation, the
divisor (D) can be 1 to 65536.
The UART programmable features include:
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
• PIO (Programmed I/O) – The processor sends or receives
• DMA (Direct Memory Access) – The DMA controller
• Supporting bit rates ranging from (f
• Supporting data formats from 7 to12 bits per frame.
• Both transmit and receive operations can be configured to
data by writing or reading I/O-mapped UATX or UARX
registers, respectively. The data is double-buffered on both
transmit and receive.
transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower priority than most DMA chan-
nels because of their relatively low service rates.
(f
generate maskable interrupts to the processor.
SCLK
/16) bits per second.
SPI Clock Rate
UART Clock Rate
=
---------------------------------- -
2
×
=
SPIBAUD
f
--------------- -
16 D
SCLK
f
SCLK
SCLK
×
ADSP-BF561
/ 1048576) to