ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 4

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

ADSP-BF561
Each MAC performs a 16-bit by 16-bit multiply in every cycle,
with an accumulation to a 40-bit result, providing 8 bits of
extended precision. The ALUs perform a standard set of arith-
metic and logical operations. With two ALUs capable of
operating on 16- or 32-bit data, the flexibility of the computa-
tion units covers the signal processing requirements of a varied
set of application needs.
Each of the two 32-bit input registers can be regarded as two 16-
bit halves, so each ALU can accomplish very flexible single 16-
bit arithmetic operations. By viewing the registers as pairs of 16-
bit operands, dual 16-bit or single 32-bit operations can be
accomplished in a single cycle. By further taking advantage of
the second ALU, quad 16-bit operations can be accomplished
simply, accelerating the per cycle throughput.
The powerful 40-bit shifter has extensive capabilities for per-
forming shifting, rotating, normalization, extraction, and
depositing of data. The data for the computational units is
found in a multi-ported register file of sixteen 16-bit entries or
eight 32-bit entries.
A powerful program sequencer controls the flow of instruction
execution, including instruction alignment and decoding. The
sequencer supports conditional jumps and subroutine calls, as
well as zero-overhead looping. A loop buffer stores instructions
locally, eliminating instruction memory accesses for tight
looped code.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from memory. The DAGs
share a register file containing four sets of 32-bit Index, Modify,
Length, and Base registers. Eight additional 32-bit registers pro-
vide pointers for general indexing of variables and stack
locations.
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. Level 2 (L2) memories are other
memories, on-chip or off-chip, that may take multiple processor
cycles to access. At the L1 level, the instruction memory holds
instructions only. The two data memories hold data, and a dedi-
cated scratchpad data memory stores stack and local variable
information. At the L2 level, there is a single unified memory
space, holding both instructions and data.
In addition, half of L1 instruction memory and half of L1 data
memories may be configured as either Static RAMs (SRAMs) or
caches. The Memory Management Unit (MMU) provides mem-
ory protection for individual tasks that may be operating on the
core and may protect system registers from unintended access.
The architecture provides three modes of operation: User mode,
Supervisor mode, and Emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin instruction set has been optimized so that 16-bit
op-codes represent the most frequently used instructions,
resulting in excellent compiled code density. Complex DSP
instructions are encoded into 32-bit op-codes, representing fully
featured multifunction instructions. Blackfin processors sup-
Rev. PrC | Page 4 of 52 | April 2004
port a limited multi-issue capability, where a 32-bit instruction
can be issued in parallel with two 16-bit instructions, allowing
the programmer to use many of the core resources in a single
instruction cycle.
The Blackfin assembly language uses an algebraic syntax for
ease of coding and readability. The architecture has been opti-
mized for use in conjunction with the VisualDSP C/C++
compiler, resulting in fast and efficient software
implementations.
MEMORY ARCHITECTURE
The ADSP-BF561 views memory as a single unified 4G-byte
address space, using 32-bit addresses. All resources including
internal memory, external memory, and I/O control registers
occupy separate sections of this common address space. The
memory portions of this address space are arranged in a hierar-
chical structure to provide a good cost/performance balance of
some very fast, low-latency memory as cache or SRAM very
close to the processor, and larger, lower-cost and performance-
memory systems farther away from the processor. The ADSP-
BF561 memory map is shown in
The L1 memory system in each core is the highest-performance
memory available to each Blackfin core. The L2 memory pro-
vides additional capacity with lower performance. Lastly, the
off-chip memory system, accessed through the External Bus
Interface Unit (EBIU), provides expansion with SDRAM, flash
memory, and SRAM, optionally accessing more than 768M
bytes of physical memory. The memory DMA controllers pro-
vide high-bandwidth data-movement capability. They can
perform block transfers of code or data between the internal
L1/L2 memories and the external memory spaces.
Internal (On-chip) Memory
The ADSP-BF561 has four blocks of on-chip memory providing
high-bandwidth access to the core.
The first is the L1 instruction memory of each Blackfin core
consisting of 16K bytes of 4-way set-associative cache memory
and 16K bytes of SRAM. The cache memory may also be config-
ured as an SRAM. This memory is accessed at full processor
speed. When configured as SRAM, each of the two 16K banks of
memory is broken into 4K sub-banks which can be indepen-
dently accessed by the processor and DMA.
The second on-chip memory block is the L1 data memory of
each Blackfin core which consists of four banks of 16K bytes
each. Two of the L1 data memory banks can be configured as
one way of a two-way set associative cache or as an SRAM. The
other two banks are configured as SRAM. All banks are accessed
at full processor speed. When configured as SRAM, each of the
four 16K banks of memory is broken into 4K sub-banks which
can be independently accessed by the processor and DMA.
The third memory block associated with each core is a 4K-byte
scratchpad SRAM which runs at the same speed as the L1 mem-
ories, but is only accessible as data SRAM (it cannot be
configured as cache memory and is not accessible via DMA).
Preliminary Technical Data
Figure
3.