ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 2

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

ADSP-BF561
TABLE OF CONTENTS
General Description ................................................. 3
REVISION HISTORY
Revision PrC:
Portable Low-Power Architecture ............................. 3
Blackfin Processor Core .......................................... 3
Memory Architecture ............................................ 4
DMA Controllers .................................................. 8
WatchDog Timers ................................................ 8
Serial Ports (SPORTs) ............................................ 9
Serial Peripheral Interface (SPI) Ports ........................ 9
UART Port .......................................................... 9
Programmable Flags (PFx) .................................... 10
Timers ............................................................. 10
Parallel Peripheral Interface ................................... 10
Dynamic Power Management ................................ 11
Voltage Regulation .............................................. 12
Clock Signals ..................................................... 13
Booting Modes ................................................... 13
Instruction Set Description ................................... 14
Internal (On-chip) Memory ................................. 4
External (Off-Chip) Memory ................................ 5
I/O Memory Space ............................................. 6
Booting ........................................................... 6
Event Handling ................................................. 6
Core Event Controller (CEC) ................................ 6
System Interrupt Controller (SIC) .......................... 6
Event Control ................................................... 7
General Purpose Mode Descriptions .................... 10
Input Mode .................................................... 10
ITU -R 656 Mode Descriptions ........................... 10
Active Video Only Mode ................................... 10
Vertical Blanking Interval Mode .......................... 11
Entire Field Mode ............................................ 11
Full-On Operating Mode – Maximum Performance . 11
Active Operating Mode – Moderate Power Savings .. 11
Hibernate Operating Mode—Maximum Static Power
Sleep Operating Mode – High Power Savings ......... 11
Deep Sleep Operating Mode – Max. Power Savings .. 11
Power Savings ................................................. 12
Savings ....................................................... 11
Rev. PrC | Page 2 of 52 | April 2004
Pin Descriptions .................................................... 16
Specifications ........................................................ 20
256-ball MBGA Pin Configurations ............................ 45
297-ball PBGA Pin Configurations ............................. 47
Outline Dimensions ................................................ 50
Outline Dimensions ................................................ 51
Ordering Guide ..................................................... 51
Development Tools .............................................. 14
Designing an Emulator-Compatible
Additional Information ........................................ 15
Recommended Operating Conditions ...................... 20
Electrical Characteristics ....................................... 20
Absolute Maximum Ratings ................................... 21
ESD Sensitivity ................................................... 21
Timing Specifications ........................................... 22
Power Dissipation ............................................... 42
Output Drive Currents ......................................... 42
Test Conditions .................................................. 42
Example System Hold Time Calculation ................... 43
Capacitive Loading .............................................. 44
Processor Board (Target) ................................... 15
Clock and Reset Timing ..................................... 23
Asynchronous Memory Read Cycle Timing ............ 24
Asynchronous Memory Write Cycle Timing ........... 25
SDRAM Interface Timing .................................. 26
External Port Bus Request and Grant Cycle Timing .. 27
Serial Ports ..................................................... 29
Serial Peripheral Interface (SPI) Port—Master Timing 34
Serial Peripheral Interface (SPI) Port—Slave Timing . 36
Universal Asynchronous Receiver-Transmitter (UART)
Timer Cycle Timing .......................................... 39
Programmable Flags Cycle Timing ....................... 40
JTAG Test And Emulation Port Timing ................. 41
Output Enable Time ......................................... 43
Output Disable Time ......................................... 43
• Edits made to pinlists and timing specification.
Parallel Peripheral Interface Timing ..................... 28
Port—Receive and Transmit Timing .................. 38
Preliminary Technical Data