ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 7

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

Preliminary Technical Data
Table 2. Peripheral Interrupt Source Reset State
Peripheral Interrupt Source
PLL wakeup
DMA1 Error
DMA2 Error
IMDMA Error
PPI1 Error
PPI2 Error
SPORT0 Error
SPORT1 Error
SPI Error
UART Error
Reserved
DMA1 0 interrupt
DMA1 1 interrupt
DMA1 2 interrupt
DMA1 3 interrupt
DMA1 4 interrupt
DMA1 5 interrupt
DMA1 6 interrupt
DMA1 7 interrupt
DMA1 8 interrupt
DMA1 9 interrupt
DMA1 10 interrupt
DMA1 11 interrupt
DMA2 0 interrupt
DMA2 1 interrupt
DMA2 2 interrupt
DMA2 3 interrupt
DMA2 4 interrupt
DMA2 5 interrupt
DMA2 6 interrupt
DMA2 7 interrupt
DMA2 8 interrupt
DMA2 9 interrupt
DMA2 10 interrupt
DMA2 11 interrupt
Timer0 interrupt
Timer1 interrupt
Timer2 interrupt
Timer3 interrupt
Timer4 interrupt
Timer5 interrupt
Timer6 interrupt
Timer7 interrupt
Timer8 interrupt
Timer9 interrupt
Timer10 interrupt
Chan
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
1
Rev. PrC | Page 7 of 52 | April 2004
IVG
IVG07
IVG07
IVG07
IVG07
IVG07
IVG07
IVG07
IVG07
IVG07
IVG07
IVG07
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
2
Table 2. Peripheral Interrupt Source Reset State (Continued)
1
2
Event Control
The ADSP-BF561 provides the user with a very flexible mecha-
nism to control the processing of events. In the CEC, three
registers are used to coordinate and control events. Each of the
registers, as follows, is 16-bits wide, while each bit represents a
particular event class:
Peripheral Interrupt Source
Timer11 interrupt
FIO0 interrupt A
FIO0 interrupt B
FIO1 interrupt A
FIO1 interrupt B
FIO2 interrupt A
FIO2 interrupt B
DMA1 write/read 0 interrupt
DMA1 write/read1 interrupt
DMA2 write/read 0 interrupt
DMA2 write/read 1 interrupt
IMDMA write/read 0 interrupt
IMDMA write/read 1 interrupt
Watchdog Timer
Reserved
Reserved
Supplemental 0
Supplemental 1
Peripheral Interrupt Channel Number
Default User IVG Interrupt
• CEC Interrupt Latch Register (ILAT) – The ILAT register
• CEC Interrupt Mask Register (IMASK) – The IMASK reg-
• CEC Interrupt Pending Register (IPEND) – The IPEND
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
may be written only when its corresponding IMASK bit is
cleared.
ister controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event
thereby preventing the processor from servicing the event
even though the event may be latched in the ILAT register.
This register may be read from or written to while in super-
visor mode. (Note that general-purpose interrupts can be
globally enabled and disabled with the STI and CLI instruc-
tions, respectively.)
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
ADSP-BF561
Chan
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
1
IVG
IVG10
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG08
IVG08
IVG09
IVG09
IVG12
IVG12
IVG13
IVG07
IVG07
IVG07
IVG07
2