ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 26

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ADSP-BF561SKBCZ600

Manufacturer Part Number
ADSP-BF561SKBCZ600
Description
DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADSP-BF561SKBCZ600

Package
256CSP-BGA
Numeric And Arithmetic Format
Fixed-Point
Maximum Speed
600 MHz
Ram Size
32 KB
Device Million Instructions Per Second
600 MIPS
ADSP-BF561
SDRAM Interface Timing
Table 16. SDRAM Interface Timing
1
Command pins include: SRAS, SCAS, SWE, SDQM, SMS3-0, SA10, SCKE.
Parameter
Timing Requirement
t
t
Switching Characteristic
t
t
t
t
t
t
t
SSDAT
HSDAT
SCLK
SCLKH
SCLKL
DCAD
HCAD
DSDAT
ENSDAT
DATA Setup Before CLKOUT
DATA Hold After CLKOUT
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
Command, ADDR, Data Delay After CLKOUT
Command, ADDR, Data Hold After CLKOUT
Data Disable After CLKOUT
Data Enable After CLKOUT
CLKOUT
DATA (IN)
DATA(OUT)
CMND ADDR
(OUT)
t
SSDAT
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Rev. PrC | Page 26 of 52 | April 2004
Figure 10. SDRAM Interface Timing
1
t
1
DCAD
t
SCLK
t
t
ENSDAT
HSDAT
t
t
DCAD
HCAD
t
SCLKL
Preliminary Technical Data
Min
2.1
0.8
7.5
2.5
2.5
0.8
1.0
t
t
D SDA T
SCLKH
t
HCAD
Max
6.0
6.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

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