ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 27

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ADSP-BF561SKBCZ600

Manufacturer Part Number
ADSP-BF561SKBCZ600
Description
DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADSP-BF561SKBCZ600

Package
256CSP-BGA
Numeric And Arithmetic Format
Fixed-Point
Maximum Speed
600 MHz
Ram Size
32 KB
Device Million Instructions Per Second
600 MIPS
Preliminary Technical Data
External Port Bus Request and Grant Cycle Timing
Table 17
bus grant operations.
Table 17. External Port Bus Request and Grant Cycle Timing
1
2
These are preliminary timing parameters that are based on worst-case operating conditions.
The pad loads for these timing parameters are 20 pF.
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
BS
BH
SD
SE
DBG
EBG
DBH
EBH
and
, 1, 2
Figure 11
A R E
B R
C L K O U T
A M S x
B G H
A B E 3 -0
A W E
B G
A D D R 2 5 -2
BR asserted to CLKOUT high setup
CLKOUT high to BR de-asserted hold time
CLKOUT low to SMS, address, and RD/WR disable
CLKOUT low to SMS, address, and RD/WR enable
CLKOUT high to BG asserted setup
CLKOUT high to BG de-asserted hold time
CLKOUT high to BGH asserted setup
CLKOUT high to BGH de-asserted hold time
describe external port bus request and
t
B S
Figure 11. External Port Bus Request and Grant Cycle Timing
Rev. PrC | Page 27 of 52 | April 2004
t
B H
t
t
t
S D
S D
S D
Min
0.0
4.6
t
t
D B G
D B H
Max
4.5
4.5
3.6
3.6
3.6
3.6
t
t
E B H
E B G
ADSP-BF561
t
t
t
S E
S E
S E
Unit
ns
ns
ns
ns
ns
ns
ns
ns

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