ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 8

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

ADSP-BF561
The SIC allows further control of event processing by providing
six 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the mode of the processor.
DMA CONTROLLERS
The ADSP-BF561 has multiple, independent DMA controllers
that support automated data transfers with minimal overhead
for the DSP core. DMA transfers can occur between the ADSP-
BF561's internal memories and any of its DMA-capable periph-
erals. Additionally, DMA transfers can be accomplished
between any of the DMA-capable peripherals and external
devices connected to the external memory interfaces, including
the SDRAM controller and the asynchronous memory control-
ler. DMA-capable peripherals include the SPORTs, SPI port,
UART, and PPI. Each individual DMA-capable peripheral has
at least one dedicated DMA channel.
The ADSP-BF561 DMA controllers support both 1-dimen-
sional (1D) and 2-dimensional (2D) DMA transfers. DMA
transfer initialization can be implemented from registers or
from sets of parameters called descriptor blocks.
• SIC Interrupt Mask Register (SIC_IMASK0, SIC_IMASK1)
• SIC Interrupt Status Register (SIC_ISTAT0, SIC_ISTAT1)
• SIC Interrupt Wakeup Enable Register (SIC_IWR0,
– This register controls the masking and unmasking of
each peripheral interrupt event. When a bit is set in the reg-
ister, that peripheral event is unmasked and will be
processed by the system when asserted. A cleared bit in the
register masks the peripheral event thereby preventing the
processor from servicing the event.
– As multiple peripherals can be mapped to a single event,
this register allows the software to determine which periph-
eral event source triggered the interrupt. A set bit indicates
the peripheral is asserting the interrupt, a cleared bit indi-
cates the peripheral is not asserting the event.
SIC_IWR1)– By enabling the corresponding bit in this reg-
ister, each peripheral can be configured to wake up the
processor, should the processor be in a powered down
mode when the event is generated.
see Dynamic Power Management on Page
Table
2.
(For more information,
11.)
Rev. PrC | Page 8 of 52 | April 2004
The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to +/- 32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
Examples of DMA types supported by the ADSP-BF561 DMA
controllers include:
In addition to the dedicated peripheral DMA channels, each
DMA Controller has four memory DMA channels provided for
transfers between the various memories of the ADSP-BF561
system. These enable transfers of blocks of data between any of
the memories—including external SDRAM, ROM, SRAM, and
flash memory—with minimal processor intervention. Memory
DMA transfers can be controlled by a very flexible descriptor-
based methodology or by a standard register-based autobuffer
mechanism.
Further, the ADSP-BF561 has a four channel Internal Memory
DMA (IMDMA) Controller. The IMDMA Controller allows
data transfers between any of the internal L1 and L2 memories.
WATCHDOG TIMERS
Each ADSP-BF561 core includes a 32-bit timer, which can be
used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the proces-
sor to a known state, via generation of a hardware reset, non-
maskable interrupt (NMI), or general- purpose interrupt, if the
timer expires before being reset by software. The programmer
initializes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must
reload the counter before it counts to zero from the pro-
grammed value. This protects the system from remaining in an
unknown state where software, which would normally reset the
timer, has stopped running due to an external noise condition
or software error.
After a reset, software can determine if the watchdog was the
source of the hardware reset by interrogating a status bit in the
timer control register, which is set only upon a watchdog gener-
ated reset.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of SCLK.
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
full or fractionally full buffer
base DMA address within a common page
Preliminary Technical Data