ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 3

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-BF561 processor is a high-performance member of
the Blackfin family of products targeting a variety of multimedia
and telecommunications applications. At the heart of this device
are two independent Analog Devices Blackfin processors. These
Blackfin processors combine a dual-MAC state-of-the-art signal
processing engine, the advantage of a clean, orthogonal RISC-
like microprocessor instruction set, and single-instruction, mul-
tiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture. The ADSP-BF561 device integrates
a general purpose set of digital imaging peripherals creating a
complete system on-chip solution for digital imaging and multi-
media applications.
The ADSP-BF561 processor has 328 KBytes of on-chip mem-
ory. Each Blackfin core includes:
• 16K Bytes of Instruction SRAM/Cache
• 16K Bytes of Instruction SRAM
• 32K Bytes of Data SRAM/Cache
• 32K Bytes of Data SRAM
• 4K Bytes of Scratchpad SRAM
FP
R7
R6
R5
R4
R3
R2
R1
R0
SP
P5
P4
P3
P2
P1
P0
SHIFTER
I3
I2
I1
I0
BARREL
8
L3
L2
L1
L0
ADDRESS ARITHMETIC UNIT
DATA ARITHMETIC UNIT
A0
16
Rev. PrC | Page 3 of 52 | April 2004
B3
B2
B1
B0
Figure 2. Blackfin Processor Core
40
M3
M2
M1
M0
8
8
DAG0
Additional on-chip memory peripherals include:
PORTABLE LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance for embedded signal processing applications.
Blackfin processors are designed in a low power and low voltage
design methodology and feature Dynamic Power Management.
Dynamic Power Management is the ability to vary both the volt-
age and frequency of operation to significantly lower the overall
power dissipation. This translates into an exponential reduction
in power dissipation providing longer battery life to portable
applications.
BLACKFIN PROCESSOR CORE
As shown in
plier/accumulators (MACs), two 40-bit ALUs, four video ALUs,
and a single shifter. The computational units process 8-bit, 16-
bit, or 32-bit data from the register file.
• 128 KBytes of Low Latency On-chip SRAM
• Four Channel Internal Memory DMA Controller
• External Memory controller with glueless support for
SDRAM, SRAM, and Flash
16
A1
40
DAG1
Figure
8
2, each Blackfin core contains two multi-
LOOP BUFFER
SEQUENCER
CONTROL
DECODE
ALIGN
UNIT
ADSP-BF561