TE28F800C3TA90 Intel, TE28F800C3TA90 Datasheet - Page 43

• Manufacturer Part Number: TE28F800C3TA90
• Description: Flash Mem Parallel 3V/3.3V 8M-Bit 512K x 16 90ns 48-Pin TSOP
• Manufacturer: Intel

Specifications of TE28F800C3TA90

• Package: 48TSOP
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Top
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 15
• Support Of Common Flash Interface: Yes
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

8.2
Datasheet
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
NOTES:
1. Write pulse width (t
2. Refer to
3. Sampled, but not 100% tested.
4. See
5. See
goes high first). Hence, t
WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence,
t
slew rate.
Table 17. Write Operations—8 Mbit Density
WPH
#
Figure 11, “AC Input/Output Reference Waveform” on page 49
Figure 9, “Write Operations Waveform” on page
= t
WHWL
Table 7, “Command Bus Operations” on page 24
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PHWL
PHEL
ELWL
WLEL
WLWH
ELEH
DVWH
DVEH
AVWH
AVEH
WHEH
EHWH
WHDX
EHDX
WHAX
EHAX
WHWL /
EHEL
VPWH
VPEH
QVVL
BHWH
BHEH
QVBL
WHGL
Sym
AC Write Characteristics
= t
/
/
/
/
/
/
/
/
/
/
EHEL
WP
) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever
= t
RP# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold Time from WE# (CE#) High
Data Hold Time from WE# (CE#) High
Address Hold Time from WE# (CE#) High
WE# (CE#) Pulse Width High
V
V
WP# Setup to WE# (CE#) Going High
WP# Hold from Valid SRD
WE# High to OE# Going Low
PP
PP
WP
WHEL
Setup to WE# (CE#) Going High
Hold from Valid SRD
= t
Parameter
= t
WLWH
EHWL
= t
.
ELEH
= t
WLEH
V
CC
= t
47.
ELWH
for valid A
Product
Density
Intel
. Similarly, write pulse width high (t
3.0 V – 3.6 V
2.7 V – 3.6 V
£
for timing measurements and maximum allowable input
IN
Advanced+ Boot Block Flash Memory (C3)
or D
Note
2,4,5
2,4,5
2,4,5
2,4,5
2,4,5
3,4,5
4,5
4,5
4,5
4,5
3,4
3,4
3,4
3,4
IN
.
Min
150
200
80
50
50
50
30
30
0
0
0
0
0
0
0
90 ns
Min
150
200
90
60
50
60
30
30
0
0
0
0
0
0
0
8 Mbit
WPH
) is defined from CE# or
Min
100
150
200
70
60
70
30
30
0
0
0
0
0
0
0
110 ns
Min
110
150
200
70
60
70
30
30
0
0
0
0
0
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
43