TE28F800C3TA90 Intel, TE28F800C3TA90 Datasheet - Page 23

• Manufacturer Part Number: TE28F800C3TA90
• Description: Flash Mem Parallel 3V/3.3V 8M-Bit 512K x 16 90ns 48-Pin TSOP
• Manufacturer: Intel

Specifications of TE28F800C3TA90

• Package: 48TSOP
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Top
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 15
• Support Of Common Flash Interface: Yes
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

£
Intel
Advanced+ Boot Block Flash Memory (C3)
4.3.1
Suspending and Resuming Erase
Since an Erase operation requires on the order of seconds to complete, an Erase Suspend command
is provided to allow erase - sequence interruption in order to read data from—or program data to—
another block in memory. Once the erase sequence is started, issuing the Erase Suspend command
to the CUI suspends the erase sequence at a predetermined point in the erase algorithm. The status
register will indicate if/when the Erase operation has been suspended. Erase-suspend latency is
specified by t
/t
.
WHRH2
EHRH2
A Read Array or Program command can now be issued to the CUI to read/program data from/to
blocks other than that which is suspended. This nested Program command can subsequently be
suspended to read yet another location. The only valid commands while Erase is suspended are
Read Status Register, Read Identifier, CFI Query, Program Setup, Program Resume, Erase
Resume, Lock Block, Unlock Block, and Lock-Down Block. During erase-suspend mode, the chip
can be placed in a pseudo - standby mode by taking CE# to V
, which reduces active current
IH
consumption.
Erase Resume continues the erase sequence when CE# = V
. Similar to the end of a standard
IL
Erase operation, the status register should be read and cleared before the next instruction is issued.
Datasheet
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