TE28F800C3TA90 Intel, TE28F800C3TA90 Datasheet - Page 25

• Manufacturer Part Number: TE28F800C3TA90
• Description: Flash Mem Parallel 3V/3.3V 8M-Bit 512K x 16 90ns 48-Pin TSOP
• Manufacturer: Intel

Specifications of TE28F800C3TA90

• Package: 48TSOP
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Top
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 15
• Support Of Common Flash Interface: Yes
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

Datasheet
(HEX)
Code
D0
C0
FF
B0
2F
Table 8. Command Codes and Descriptions
40
20
70
50
90
60
01
98
Program Suspend
Block Lock, Block
Program Set-Up
Lock-Down Set-
Erase Suspend
Program/Erase
Erase Confirm
Device Mode
Erase Set-Up
Unlock, Block
Unlock Block
Read Status
Clear Status
Read Array
Lock-Down
Lock-Block
Protection
Identifier
Resume
Register
Register
Program
Set-Up
Query
Read
CFI
Up
This command places the device in read-array mode, which outputs array data on the data
pins.
This is a two - cycle command. The first cycle prepares the CUI for a program operation. The
second cycle latches addresses and data information and initiates the WSM to execute the
Program algorithm. The flash outputs status-register data when CE# or OE# is toggled. A Read
Array command is required after programming to read array data. See
Mode” on page
This is a two - cycle command. Prepares the CUI for the Erase Confirm command. If the next
command is not an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of
the status register to a “1,” (b) place the device into the read-status-register mode, and (c) wait
for another command. See
If the previous command was an Erase Set-Up command, then the CUI will close the address
and data latches and begin erasing the block indicated on the address pins. During program/
erase, the device will respond only to the Read Status Register, Program Suspend and Erase
Suspend commands, and will output status-register data when CE# or OE# is toggled.
If a Program or Erase operation was previously suspended, this command will resume that
operation.
If the previous command was Block Unlock Set-Up, the CUI will latch the address and unlock
the block indicated on the address pins. If the block had been previously set to Lock-Down, this
operation will have no effect. (See
Issuing this command will begin to suspend the currently executing Program/Erase operation.
The status register will indicate when the operation has been successfully suspended by
setting either the program-suspend SR[2] or erase-suspend SR[6] and the WSM status bit
SR[7] to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the
state of all input-control pins except RP#, which will immediately shut down the WSM and the
remainder of the chip if RP# is driven to V
This command places the device into read-status-register mode. Reading the device will
output the contents of the status register, regardless of the address presented to the device.
The device automatically enters this mode after a Program or Erase operation has been
initiated. See
The WSM can set the block-lock status SR[1], V
erase-status SR[5] bits in the status register to “1,” but it cannot clear them to “0.” Issuing this
command clears those bits to “0.”
Puts the device into the read-identifier mode so that reading the device will output the
manufacturer/device codes or block-lock status. See
page
Prepares the CUI for block-locking changes. If the next command is not Block Unlock, Block
Lock, or Block Lock-Down, then the CUI will set both the program and erase-status-register
bits to indicate a command-sequence error. See
If the previous command was Lock Set-Up, the CUI will latch the address and lock the block
indicated on the address pins. (See
If the previous command was a Lock-Down Set-Up command, the CUI will latch the address
and lock-down the block indicated on the address pins. (See
Puts the device into the CFI-Query mode so that reading the device will output Common Flash
Interface information. See
This is a two-cycle command. The first cycle prepares the CUI for a program operation to the
protection register. The second cycle latches addresses and data information and initiates the
WSM to execute the Protection Program algorithm to the protection register. The flash outputs
status-register data when CE# or OE# is toggled. A Read Array command is required after
programming to read array data. See
19.
Section 4.1.4, “Read Status Register” on page
21.
Section 4.1.3
Section 4.3, “Erase Mode” on page
Intel
Section
Command Description
Section
£
Section
Advanced+ Boot Block Flash Memory (C3)
and
IL
5.1)
. See Sections 3.2.5.1 and 3.2.6.1.
5.1)
Appendix C, “Common Flash
5.5.
PP
Section 5.0, “Security Modes” on page
Status SR[3], program status SR[4], and
Section 4.1.2, “Read Identifier” on
20.
Section
22.
5.1)
Section 4.2, “Program
Interface”.
27.
25