T5760NTGS Atmel, T5760NTGS Datasheet - Page 8

• Manufacturer Part Number: T5760NTGS
• Manufacturer: Atmel

Specifications of T5760NTGS

• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

6. Polling Circuit and Control Logic
7. Basic Clock Cycle of the Digital Circuitry
8
T5760/T5761
Figure 5-2.
The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor-
responding transmitter. This is achieved via the polling circuit. This circuit enables the signal
path periodically for a short time. During this time the bit-check logic verifies the presence of a
valid transmitter signal. Only if a valid signal is detected, the receiver remains active and trans-
fers the data to the connected microcontroller. If there is no valid signal present, the receiver is
in sleep mode most of the time resulting in low current consumption. This condition is called poll-
ing mode. A connected microcontroller is disabled during that time.
All relevant parameters of the polling logic can be configured by the connected microcontroller.
This flexibility enables the user to meet the specifications in terms of current consumption, sys-
tem response time, data rate etc.
Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It
can be either operated by a single bi-directional line to save ports to the connected microcontrol-
ler or it can be operated by up to five uni-directional ports.
The complete timing of the digital circuitry and the analog filtering is derived from one clock. This
clock cycle T
cuit. According to section
is defined by the RF input signal (f
oscillator (f
and T
T
Clk
• Timing of the polling circuit including bit check
• Timing of the analog and digital signal processing
• Timing of the register programming
• Frequency of the reset marker
• IF filter center frequency (f
controls the following application-relevant parameters:
Clk
= 1.961 µs for f
LO
Clk
). The basic clock cycle is T
Wide Band Receiving Frequency Response
is derived from the crystal oscillator (XTO) in combination with a divide by 14 cir-
RF
-100.0
-20.0
-30.0
-40.0
-60.0
-80.0
-90.0
-50.0
-70.0
-10.0
0.0
“RF Front End” on page
= 915 MHz.
-12.0
IF0
)
-9.0
RFin
) which also defines the operating frequency of the local
-6.0
Clk
= 14/f
-3.0
df (MHz)
XTO
4, the frequency of the crystal oscillator (f
0.0
giving T
3.0
6.0
Clk
= 2.066 µs for f
9.0
12.0
RF
4561C–RKE–05/05
= 868.3 MHz
XTO
)