T5760NTGS Atmel, T5760NTGS Datasheet - Page 19

• Manufacturer Part Number: T5760NTGS
• Manufacturer: Atmel

Specifications of T5760NTGS

• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Figure 9-3.
Figure 9-4.
4561C–RKE–05/05
Dem_out
Data_out (DATA)
DATA_CLK
Dem_out
Data_out (DATA)
DATA_CLK
Data Clock Disappears Because of a Logical Error
Output of the Data Clock After a Successful Bit Check
The delay of the data clock is calculated as follows: t
t
depends on the capacitive load C
falling edge, t
on page 20
Data_Out, the data clock is issued after an additional delay t
Note that the capacitive load at pin DATA is limited. If the maximum tolerated capacitive load at
pin DATA is exceeded, the data clock disappears (see section
Delay1
is the delay between the internal signals Data_Out and Data_In. For the rising edge, t
'1'
'1'
Receiving mode,
bit check active
Bit check ok
and
Delay1
'1'
'1'
Figure 13-2 on page
depends additionally on the external voltage V
Receiving mode,
data clock control
logic active
'1'
'1'
'0'
'1'
L
'1'
'1'
at pin DATA and the external pull-up resistor R
Data
27). When the level of Data_In is equal to the level of
Start bit
Data
'1'
'0'
Logical error (Manchester code violation)
Receiving mode,
data clock control
logic active
'?'
'1'
Delay
'0'
'1'
= t
Delay1
'0'
Delay2
'0'
Receiving mode,
bit check aktive
“Data Interface” on page
.
+ t
'1'
'1'
X
Delay2
(see
T5760/T5761
'0'
'0'
Figure
9-5,
pup
Figure 9-6
. For the
28).
Delay1
19