T5760NTGS Atmel, T5760NTGS Datasheet - Page 12

• Manufacturer Part Number: T5760NTGS
• Manufacturer: Atmel

Specifications of T5760NTGS

• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Figure 8-4.
12
Bit check
IC_ACTIVE
Dem_out
Bit-check-
counter
(Lim_min = 14, Lim_max = 24)
T5760/T5761
Timing Diagram During Bit Check
Start-up mode
T
For best noise immunity it is recommended to use a low span between T
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A
‘11111...’ or a ‘10101...’ sequence in Manchester or Bi-phase is a good choice concerning that
advice. A good compromise between receiver sensitivity and susceptibility to noise is a time win-
dow of ±30% regarding the expected edge-to-edge time t
contain various edge-to-edge time periods, the bit-check limits must be programmed according
to the required span.
The bit-check limits are determined by means of the formula below.
T
T
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using above formulas, Lim_min and Lim_max can be determined according to the required
T
mum edge-to-edge time t
“Receiving Mode” on page
value of the upper limit is Lim_max = 63.
If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits (N
prevent switching to receiving mode due to noise.
Figure 8-7 on page
bit-check limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing
circuits are enabled during T
fined during that period. When the bit check becomes active, the bit-check counter is clocked
with the cycle T
Figure 8-7 on page 14
is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
ure 8-8 on page 14
bit check also fails if CV_Lim reaches Lim_max. This is illustrated in
Start-up
0
Lim_min
Lim_max
Lim_min
, T
= Lim_min
= (Lim_max – 1)
1
Lim_max
2 3 4 5 6
XClk
and T
T
.
7 8 1
XClk
the bit check fails as the value CV_Lim is lower than the limit Lim_min. The
14,
T
XClk
shows how the bit check proceeds if the bit-check counter value CV_Lim
XClk
2
Figure 8-8
3
. The time resolution defining T
T
4 5
ee
13. The lower limit should be set to Lim_min
Startup
XClk
(t
6 7 8 9
DATA_L_min
. The output of the ASK/FSK demodulator (Dem_out) is unde-
1/2 Bit
and
10
Bit-check mode
11 12 13 14
Figure 8-9 on page 15
T
Bit-check
, t
DATA_H_min
15 16 17 18 1 2 3 4 5 6
Bit check ok
) is defined according to the section
Lim_min
ee
. Using pre-burst patterns that
and T
1/2 Bit
7 8 9 10 11 12 13 14 15 1 2 3 4
illustrate the bit check for the
Figure 8-9 on page
Lim_max
Bit check ok
Lim_min
10. The maximum
is T
1/2 Bit
XClk
4561C–RKE–05/05
and T
. The mini-
Bit-check
15.
Lim_max
Fig-
) to
.