21154BC Intel, 21154BC Datasheet - Page 35

• Manufacturer Part Number: 21154BC
• Manufacturer: Intel

Specifications of 21154BC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

21.
22.
23.
24.
25.
26.
27.
21154 PCI-to-PCI Bridge Specification Update
Note: Refer to Errata #7 previously in this document for an explanation of an added external buffer on the
Section 18.0, Table 51, 304-Point 2-Layer PBGA Package Dimensions
The maximum value for symbol aaa, dimension coplanarity has been changed from 0.15 mm to a
value of 0.2 mm.
Section 2.5, Secondary Bus Arbitration Signals, Table 8
This sentence is added to the end of the description for s_req_l <8:0>:
This sentence is added to the end of the description for s_gnt_l<8:0>:
Section 2.9, Miscellaneous Signals, Table 12
This sentence is added at the end of the description for S_m66ena:
Updated Version of PCI Local Bus Specification
All places in the 21154 Hardware Bridge Hardware Implementation Application Note where the
PCI Local Bus Specification is mentioned was updated from version 2.1 to version 2.2.
Section 4.1, Updated s_clk and p_clk description
The first two paragraphs and the first bullet in Section 4.1 now appear as follows:
4.1 21154 Clocking Domains
The 21154 has two clocking domains: one for the primary PCI interface and one for the secondary
PCI interface. Each PCI interface has a separate clock input. The primary interface is controlled by
the primary clock input, p_clk, and the secondary interface and arbiter is controlled by the
secondary clock input, s_clk.
The edge relationship between s_clk and p_clk is well defined. The relationship between the p_clk
and s_clk inputs has the following restrictions:
Section 4.2, Updated Clock Outputs
The first bulleted item in Section 4.2 now appears as follows:
Section 4.4.1, Added Note at End of Section.
The note added to the end of Section 4.4.1 appears as follows:
output of gpio <2> to use this feature at 66 MHz.
•
•
“When the secondary bus is set to operate at 66 MHz, s_req_l <8:4> is disabled.”
“When the secondary bus is set to operate at 66 MHz, s_gnt_1 <8:4> is disabled.”
“When the secondary bus is set to operate at 66 MHz, s_req_l <8:4> and s_gnt_1<8:4> are
disabled.”
The 21154 operates at a maximum frequency of 66 MHz, and s_clk always operates at the
same frequency or half the frequency of p_clk.
All clock outputs operate at the same or half the frequency as p_clk.
Documentation Changes
Intel Confidential35