21154BC Intel, 21154BC Datasheet - Page 20

• Manufacturer Part Number: 21154BC
• Manufacturer: Intel

Specifications of 21154BC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Errata
Implication:
Workaround:
Status:
8.
Problem:
Implication:
Workaround:
Status:
9.
Problem:
20Intel Confidential
Note: For more information, see
At 66 MHz the setup time mismatch between the shift register parallel inputs and PE# pin and gpio
pins may cause the shift register to be incorrectly loaded. This could result in the secondary clocks
to be incorrectly disabled.
In order to provide an appropriate setup time, a buffer must be added to delay gpio<2> with respect
to gpio<0>. This buffer (or buffers) provides the delay for gpio<2> to correctly load the parallel
data inputs of 74F166 registers. A setup time of at least 3ns is required at the shift register for PE#
to load.
Operation
No Fix
Bus Conflict Occurs During Configuration on AGP Port of Some Chip Sets.
The 21154 Bridge accepts type zero configuration cycles on its primary bus. It also accepts Type 1
configuration cycles on its primary bus and forwards them, if they are addressed to a bus number
between its secondary and subsequent bus numbers, which are assigned to the bridge by system
software. The secondary and subsequent bus number registers are set to zero by reset. Some
chipsets supporting AGP use Type 1 configuration cycles to program themselves. The chipset has
set its own address to be bus 0, device 0. Unfortunately, this creates a conflict if the bridge's
downstream bus number registers have not yet been programmed to a non-zero value. This conflict
occurs when both the chipset and bridge respond to Type One Configuration cycles to bus 0
resulting in bus contention.
Both the AGP interface and the 21154 Bridge will respond to the same Type 1 bus transaction
causing bus signal contention.
None
Fixed
21154AE/BE May Experience Performance Problems or Hangs when P_VIO
= 3.3V
Intel has received reports of performance problems due to excessive retries and hangs in a few
applications when P_VIO and/or S_VIO =3.3V. The retry issue has been observed in several types
Video, Fibre Channel and Gigabit Ethernet modules with the time to failure ranging from 7 minutes
to 39 hours.
The symptom of this issue is that a delayed read is initiated on the primary bus. It is immediately
responded to with retry and stored as a CAM entry. The request is played out on the secondary bus
and the device receives the data. The CAM entry becomes corrupt due to noise on the core ground.
This causes the read request on the primary bus to match the CAM entry, but the bridge does not
respond with the data. As the CAM entry is matched, no additional read request is made on the
secondary bus, but the primary bus never receives the data, only retries. This causes the initiating
master to continue to retry the read, making no progress. The 21154 will eventually discard that
read data when the primary master timeout timer expires (2
read transaction is then reinitiated on the primary bus and usually completes normally. This causes
a 30.7 µs or 983 µs delay (at 33MHz) depending on the setting of the primary master timeout bit.
The same issue and scenario has also been reported on delayed reads from the secondary bus to the
primary bus.
The root cause is due to changes in the internal grounding scheme implemented in the
21154AE/BE - an approximate 400mV reduction in the noise immunity occurred in the CAM
circuitry. The data stored within the CAM (Content Addressable Memory) circuitry becomes
in this specification update.
Section 10.2.1, Mask and Load Shift Timing Events for 66 MHz
21154 PCI-to-PCI Bridge Specification Update
10
or 2
15
clock cycles). The delayed