21154BC Intel, 21154BC Datasheet - Page 15

• Manufacturer Part Number: 21154BC
• Manufacturer: Intel

Specifications of 21154BC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Errata
1.
Problem:
Implication:
Workaround:
Status:
21154 PCI-to-PCI Bridge Specification Update
Note: The FW21154BE worst case slow condition 2 includes the very slow processing corner, 108
Note: Refer to the 21154 PCI-to-PCI Bridge Specification Update Errata table for current errata. All
Tval Timing Issues When Running at 66 MHz for All PCI Signals. Tval timing
improved on the 21154BE.
This problem exists for parts with REV_ID 5 and REV_ID 0.
Two worst-case slow conditions exist. The 21154BC and 21154BE were tested under two different
sets of worst-case slow conditions.
Table 2. Definition of Worst Case Slow Conditions
a.
Table 3. Comparison of the 21154BC and the 21154BE Performance
This miss for Tval on PCI control signals may reduce total flight time (Tprop) when running at
66 MHz. The 21154BE meets or exceeds the 21154BC performance under the worst-case slow
conditions.
junction temperature, no airflow, 4 layer coupon, 3.0 V Vdd, and bus switched data (all 1s and all
0s flowing upstream from a fully loaded secondary) with no interrupts. Any improvement in the
thermal factors (Oja), board design, Vdd, data transition density, and interrupt density and Tval
will be < 6.0 ns at 85
There are no workarounds for this erratum.
errata listed are fixed in the 21154AE/BE version except for Errata #1, #2, and #7.
No
Condition 1
Condition 2
temperature, no airflow, 4 layer coupon, 3.0 V V
from a fully loaded secondary) with no interrupts.
V
dd
Fix: See
The FW21154BE worst case slow condition 2 includes the very slow processing corner, 108
, data transition density, and interrupt density and Tval will be < 6.0 ns at 85
Worst-Case Slow
21154BC
21154BC
21154BE
21154BE
Product
a
“Summary Table of Changes” on page
o
C junction temperature.
85
108
Worst-case Slow
T
test
Condition
[T
dd
1
2
1
2
j
, and bus switched data (all 1s and all 0s flowing upstream
] (
Any improvement in the thermal factors (Oja), board design,
o
C)
10.
S - slow
SS - very slow
6.5
No data
<6.4
7.35
Process Variation
(Intel Defined)
Tval V_V (ns)
o
C junction temperature.
o
3.0
3.0
8.0
No data
<6.25
7.35
C junction
Intel Confidential15
Tval Z_V (ns)
V
dd
(V)
Errata
o
C