21154BC Intel, 21154BC Datasheet - Page 16

• Manufacturer Part Number: 21154BC
• Manufacturer: Intel

Specifications of 21154BC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Errata
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16Intel Confidential
Hold Time Issues for All PCI Signals (Both Bused and Control) on the 21154.
This problem exists for parts with REV_ID 2, REV_ID 5 and REV_ID 0.
The PCI Local Bus Specification, Revision 2.2, specifies a Hold time of 0 ns in Section 7.6.4.2. The
21154AB requires a minimum hold time of 1.4 ns. Both the 21154AC/BC and 21154AE/BE
require a minimum hold time of 1.375 ns.
Most PCI devices will function properly with this difference to the Hold time specification.
There are no workarounds for this erratum.
No
Setup Issues With PCI Control Signals When Running at 66 MHz on the
21154BC.
This problem was originally believed to exist for parts with REV_ID 5.
Setup time issues on the following 66 MHz PCI control signals: p_frame_l, p_irdy_l, p_trdy_l,
s_frame_l, s_irdy_l, s_trdy_l. The PCI Local Bus Specification, Revision 2.2, specifies a Setup
time of 3 ns for all devices when running at 66 MHz in Section 7.6.4.2. The 21154BC requires a
minimum worst-case setup time of 4.5 ns.
The Tsetup specification miss on PCI control signals must be considered in the overall timing
budget for designs that use this product, and may reduce total flight time (Tprop) when running at
66 MHz.
This errata was caused by a test-fixture problem and is invalid.
Fixed
Clamp Circuit May Not Function Properly Under All Conditions
This problem has been found on parts with REV_ID 5. When either the primary or secondary vio
pins are connected to 3.3 volts, the 21154’s clamping circuit may not function properly.
Dependent on the application environment, oscillations or “ringing” have been observed on some
PCI control signals (for example, STOP#). The circuitry to generate the input clamp voltages of
both the 21154AC and 21154 BC is different than that of the 21154AB.
When the application topology allows it (short bus lengths, direct etch runs), connecting 3.3 volts
to these pins should produce desired results. The use of p_vio and s_vio for both the 21154AC and
21154BC will be determined by the customer application. Designs that adhere to the “Expansion
Board Specification” of the PCI Local Bus Specification, Revision 2.2 are not affected. Designs
whose topology might include long bus lengths might find that connecting s_vio or p_vio to 5 volts
leads to improved signal integrity for the corresponding bus. As such, Intel recommends thorough
signal integrity analyses prior to a decision on which voltage to connect to these pins.
If there is any 5-volt PCI device on a bus segment, the vio pin for that segment should be tied to the
5 volt supply.
Fixed
Fix: See
“Summary Table of Changes” on page
21154 PCI-to-PCI Bridge Specification Update
10.