21154BC Intel, 21154BC Datasheet - Page 28

• Manufacturer Part Number: 21154BC
• Manufacturer: Intel

Specifications of 21154BC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Documentation Changes
6.
7.
8.
Figure 5.
28Intel Confidential
Note: During normal 21154 operation the JTAG logic must be disabled by pulling trst_l low using a 5K
Note: During normal 21154 operation the JTAG logic must be disabled by pulling trst_l low using a 5K
Section 4.3, Paragraph 1
Section 4.3, Paragraph 1 is changed to read as follows:
Some versions of the 21154 support 66 MHz operation. Versions marked 21154Ax are not tested to
be 66 MHz capable. Versions of the 21154 marked 21154Bx are capable of 66 MHz operation.
Section 16.7, Initialization, Paragraph 1
This section has been changed to:
The test access port controller and the instruction register output latches are initialized and JTAG is
disabled while the trst_l input is asserted low. While signal trst_l is low, the test access port controller
enters the test-logic reset state. This results in the instruction register being reset which holds the
bypass register instruction. During test-logic reset state, all JTAG test logic is disabled and the device
performs normal functions. The test access port controller leaves this state only after trst_l (low) goes
high and an appropriate JTAG test operation sequence is sent on the tms and tck pins.
For the 21154 to operate properly, the JTAG logic must be reset. There are two ways to reset this
logic:
resistor.
Section 5.1, Initialization, Description
This section has been changed to:
The test access port controller and the instruction register output latches are initialized and JTAG is
disabled while the trst_l input is asserted low (see Figure 5). While signal trst_l is low, the test
access port controller enters the test-logic reset state. This results in the instruction register being
reset which holds the bypass register instruction. During test-logic reset state, all JTAG test logic is
disabled, and the device performs normal functions. The test access port controller leaves this state
only after trst_l (low) goes high and an appropriate JTAG test operation sequence is sent on the tms
and tck pins.
For the 21154 to operate properly, the JTAG logic must be reset. There are two ways to reset this
logic:
Signal trst_l States
ohm resistor.
•
•
•
•
The controller will reset asynchronously with the assertion of TRST_L.
The controller will reset synchronously after five TCK clock cycles, with TMS held high.
The controller will reset asynchronously with the assertion of trst_l.
The controller will reset synchronously after five TCK clock cycles, with TMS held high..
trst_l
JTAG Reset
21154 PCI-to-PCI Bridge Specification Update
JTAG Enabled
A7805-01