PI7C8154BNA Pericom Semiconductor, PI7C8154BNA Datasheet - Page 85
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PI7C8154BNA
Manufacturer Part Number
PI7C8154BNA
Description
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C8154BNA.pdf
(111 pages)
Specifications of PI7C8154BNA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
85C
Package Type
BGA
Rad Hardened
No
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C8154BNAE
Manufacturer:
PERICOM
Quantity:
20 000
06-0008
14.1.30
14.1.31
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h
ARBITER CONTROL REGISTER – OFFSET 40h
Bit
31-28
Bit
0
1
3:2
4
5
7:6
8
15:9
Bit
24:16
25
Function
Reserved
Function
Reserved
Memory Write
Disconnect
Control
Reserved
Secondary Bus
Prefetch Disable
Live Insertion
Mode
Reserved
Chip Reset
Reserved
Function
Arbiter Control
Priority of
Secondary
Interface
Type
R/O
Type
R/O
R/W
R/O
R/W
R/W
R/O
R/WR
R/O
Type
R/W
R/W
Page 85 of 111
Description
Reserved. Returns 0 when read. Reset to 0.
Description
Reserved. Returns 0 when read. Reset to 0
Controls when the bridge (as a target) disconnects memory write
transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Controls the bridge’s ability to prefetch during upstream memory read
transactions
0: Bridge prefetches and does not forward byte enable bits during
upstream memory read transactions.
1: Bridge requests only 1 DWORD from the target and forwards read
byte enable bits during upstream memory reads.
Reset to 0
Enables control of transaction forwarding
0: GPIO[3] has no effect on the I/O, memory, and master enable bits
1: If GPIO[3] is set to input only, this bit enables GPIO[3] to mask the
I/O enable, memory enable, and master enable bits to 0. These bits are
masked when GPIO[3] is driven HIGH. As a result, PI7C8154 stops
accepting I/O and memory transactions.
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Controls the chip and secondary bus reset.
0: Bridge is ready for operation
1: Causes Bridge to perform a chip reset
Reserved. Returns 0 when read. Reset to 0.
Description
Each bit controls whether a secondary bus master is assigned to the high
priority group or the low priority group.
Bits [24:16] correspond to request inputs S_REQ[8:0]
0: low priority
1: high priority
Reset to 0
Controls whether the secondary interface of the bridge is in the high
priority group or the low priority group.
0: low priority
1: high priority
Reset to 1
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B