PI7C8154BNA Pericom Semiconductor, PI7C8154BNA Datasheet - Page 60

• Manufacturer Part Number: PI7C8154BNA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNA

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

06-0008
5.4
Table 5-6 ASSERTION OF S_PERR#
Note: x=don’t care
Table 5-7 shows assertion of P_SERR#. This signal is set under the following conditions:
Table 5-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS
Note: x=don’t care
SYSTEM ERROR (SERR#) REPORTING
PI7C8154B uses the P_SERR# signal to report conditionally a number of system error conditions
in addition to the special case parity error conditions described in Section 5.2.3.
Whenever assertion of P_SERR# is discussed in this document, it is assumed that the following
conditions apply:
1 (de-asserted)
0 (asserted)
1
1
1
1
1
0
1
1
0
0
1 (de-asserted)
1
1
1
1
0
0
1
1
1
1
1
2
2
3
(asserted)
PI7C8154B detects a data parity error on the secondary bus or detects P_PERR# asserted
during the completion phase of an upstream delayed write transaction on the target (primary)
bus.
PI7C8154B has detected P_PERR# asserted on an upstream posted write transaction or
S_PERR# asserted on a downstream posted write transaction.
PI7C8154B did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response bit on the
bridge control register must both be set.
The SERR# enable bit must be set in the command register.
S_PERR#
P_SERR#
2
=The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
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Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Direction
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
Was Detected
Was Detected
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
x / x
x / 1
x / x
x / x
x / x
x / x
x / x
x / 1
x / x
x / x
1 / 1
x / x
x / x
x / x
x / x
x / x
1 / 1
1 / 1
x / x
x / x
x / x
x / x
x / 1
x / x
Primary/ Secondary Parity
Primary / Secondary Parity
Error Response Bits
Error Response Bits
PCI-to-PCI BRIDGE
PI7C8154B