PI7C8154BNA Pericom Semiconductor, PI7C8154BNA Datasheet - Page 83
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PI7C8154BNA
Manufacturer Part Number
PI7C8154BNA
Description
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C8154BNA.pdf
(111 pages)
Specifications of PI7C8154BNA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
85C
Package Type
BGA
Rad Hardened
No
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C8154BNAE
Manufacturer:
PERICOM
Quantity:
20 000
06-0008
14.1.26
14.1.27
14.1.28
14.1.29
CAPABILITY POINTER REGISTER – OFFSET 34h
INTERRUPT LINE REGISTER – OFFSET 3Ch
INTERRUPT PIN REGISTER – OFFSET 3Ch
BRIDGE CONTROL REGISTER – OFFSET 3Ch
Bit
7:0
Bit
7:0
Bit
15:8
Bit
16
17
18
Function
Enhanced
Capabilities Port
Pointer
Function
Interrupt Line
Function
Interrupt Pin
Function
Parity Error
Response
S_SERR# enable
ISA enable
Type
R/O
Type
R/W
Type
R/O
Type
R/W
R/W
R/W
Page 83 of 111
Description
Enhanced capabilities port offset pointer. Read as DCh to indicate that
the first item resides at that configuration offset.
Reset to DCh.
Description
For POST to program to FFh, indicating that the bridge does not
implement an interrupt pin.
Reset to 0.
Description
Interrupt pin not supported on the bridge.
Reset to 0.
Description
Controls the bridge’s response to parity errors on the secondary interface.
0: ignore address and data parity errors on the secondary interface
1: enable parity error reporting and detection on the secondary interface
Reset to 0
Controls the forwarding of S_SERR# to the primary interface.
0: disable the forwarding of S_SERR# to primary interface
1: enable the forwarding of S_SERR# to primary interface
Reset to 0
Modifies the bridge’s response to ISA I/O addresses, applying only to
those addresses falling within the I/O base and limit address registers and
within the first 64KB of PCI I/O space.
0: forward all I/O addresses in the range defined by the I/O base and I/O
limit registers
1: blocks forwarding of ISA I/O addresses in the range defined by the I/O
base and I/O limit registers that are in the first 64KB of I/O space that
address the last 768 bytes in each 1KB block. Secondary I/O transactions
are forwarded upstream if the address falls within the last 768 bytes in
each 1KB block
Reset to 0
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B