PI7C8154BNA Pericom Semiconductor, PI7C8154BNA Datasheet - Page 84
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PI7C8154BNA
Manufacturer Part Number
PI7C8154BNA
Description
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C8154BNA.pdf
(111 pages)
Specifications of PI7C8154BNA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
85C
Package Type
BGA
Rad Hardened
No
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C8154BNAE
Manufacturer:
PERICOM
Quantity:
20 000
06-0008
Bit
19
20
21
22
23
24
25
26
27
Function
VGA enable
Reserved
Master Abort
Mode
Secondary
Interface Reset
Fast Back-to-
Back Enable
Primary Master
Timeout
Secondary
Master Timeout
Master Timeout
Status
Discard Timer
P_SERR# enable
Type
R/W
R/O
R/W
R/W
R/W
R/W
R/W
R/WC
R/W
Page 84 of 111
Description
Controls the bridge’s response to VGA compatible addresses.
0: does not forward VGA compatible memory and I/O addresses from
primary to secondary
1: forward VGA compatible memory and I/O addresses from primary to
secondary regardless of other settings
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Control’s bridge’s behavior responding to master aborts on secondary
interface.
0: does not report master aborts (returns FFFF_FFFFh on reads and
discards data on writes)
1: reports master aborts by signaling target abort if possible or by the
assertion of P_SERR# if enabled
Reset to 0
Controls the assertion of S_RESET# signal pin on the secondary interface
0: does not force the assertion of S_RESET# pin
1: forces the assertion of S_RESET#
Reset to 0
Controls bridge’s ability to generate fast back-to-back transactions on the
secondary interface.
0: does not allow fast back-to-back transactions on the secondary
1: enables fast back-to-back transactions on the secondary
Reset to 0
Determines the maximum number of PCI clock cycles the bridge waits
for an initiator on the primary interface to repeat a delayed transaction
request.
0: Primary discard timer counts 2
1: Primary discard timer counts 2
Reset to 0
Determines the maximum number of PCI clock cycles the bridge waits
for an initiator on the primary interface to repeat a delayed transaction
request.
0: Primary discard timer counts 2
1: Primary discard timer counts 2
Reset to 0
This bit is set to 1 when either the primary master timeout counter or
secondary master timeout counter expires.
Reset to 0
This bit is set to 1 and P_SERR# is asserted when either the primary
discard timer or the secondary discard timer expire.
0: P_SERR# is not asserted on the primary interface as a result of the
expiration of either the Primary Discard Timer or the Secondary Discard
Timer.
1: P_SERR# is asserted on the primary interface as a result of the
expiration of either the Primary Discard Timer or the Secondary Discard
Timer.
Reset to 0
15
10
15
10
PCI clock cycles.
PCI clock cycles.
PCI clock cycles.
PCI clock cycles.
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B