PI7C8154BNA Pericom Semiconductor, PI7C8154BNA Datasheet - Page 43

• Manufacturer Part Number: PI7C8154BNA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNA

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

06-0008
2.11.4.3
3
3.1
3.2
TARGET ABORT
PI7C8154B returns a target abort to an initiator when one of the following conditions is met:
ADDRESS DECODING
PI7C8154B uses three address ranges that control I/O and memory transaction forwarding. These
address ranges are defined by base and limit address registers in the configuration space. This
chapter describes these address ranges, as well as ISA-mode and VGA-addressing support.
ADDRESS RANGES
PI7C8154B uses the following address ranges that determine which I/O and memory transactions
are forwarded from the primary PCI bus to the secondary PCI bus, and from the secondary bus to
the primary bus:
Transactions falling within these ranges are forwarded downstream from the primary PCI bus to the
secondary PCI bus. Transactions falling outside these ranges are forwarded upstream from the
secondary PCI bus to the primary PCI bus.
No address translation is required in PI7C8154B. The addresses that are not marked for
downstream are always forwarded upstream.
I/O ADDRESS DECODING
PI7C8154B uses the following mechanisms that are defined in the configuration space to specify
the I/O address space for downstream and upstream forwarding:
This section provides information on the I/O address registers and ISA mode Section 3.4 provides
information on the VGA modes.
To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the
command register in configuration space. All I/O transactions initiated on the primary bus will be
ignored if the I/O enable bit is not set. To enable upstream forwarding of I/O transactions, the
PI7C8154B is returning a target abort from the intended target.
When PI7C8154B returns a target abort to the initiator, it sets the signaled target abort bit in
the status register corresponding to the initiator interface.
Two 32-bit I/O address ranges
Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges
Two 32-bit prefetchable memory address ranges
I/O base and limit address registers
The ISA enable bit
The VGA mode bit
The VGA snoop bit
Page 43 of 111
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B