PI7C8154BNA Pericom Semiconductor, PI7C8154BNA Datasheet - Page 35

• Manufacturer Part Number: PI7C8154BNA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNA

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

06-0008
2.9
2.9.1
2.9.2
that use special cycles ignore the address and decode only the bus command. The data phase
contains the special cycle message. The transaction is forwarded as a delayed transaction, but in
this case the target response is not forwarded back (because special cycles result in a master abort).
Once the transaction is completed on the target bus, through detection of the master abort
condition, PI7C8154B responds with TRDY# to the next attempt of the con-figuration transaction
from the initiator. If more than one data transfer is requested, PI7C8154B responds with a target
disconnect operation during the first data phase.
64-BIT OPERATION
Both the primary and secondary interfaces of the PI7C8154B support 32-bit operation and 64-bit
operation. This chapter describes how to use the 64-bit operations as well as the conditions that go
along with it.
64-BIT AND 32-BIT TRANSACTIONS INITIATED BY PI7C8154B
64-bit transactions are requested by asserting P_REQ64# on the primary and S_REQ64# on the
secondary during the address phase. REQ64# is asserted and deasserted during the same cycles as
FRAME#. Under certain conditions, PI7C8154B does not use the 64-bit extension when initiating
transactions. In this case, REQ64# is not asserted.
If REQ64# is not asserted, the transaction is initiated as a 32-bit transaction when any of the
following conditions are met:
64-BIT TRANSACTIONS – ADDRESS PHASE
When a transaction using the primary bus 64-bit extension is a single address cycle, the upper 32-
bits of the address, AD[63:32], are assumed to be 0 and CBE[7:4] are not defined but driven to
valid logic levels during the address phase.
When a transaction using the primary bus 64-bit extension is a dual address cycle, the upper 32-bit
of the address, AD[63:32], contain the upper 32-bits of the address and CBE[7:4] contain memory
bus command during both address phases. A 64-bit target then has the opportunity to decode the
entire 64-bit address and bus command after the first address phase. A 32-bit target needs both
address phases to decode the full address and bus command.
P_REQ64# was not asserted by the primary during reset (64-bit extension not supported on the
primary) for upstream transactions only
PI7C8154B is initiating an I/O transaction
PI7C8154B is initiating a special cycle transaction
PI7C8154B is initiating a configuration transaction
PI7C8154B is initiating a nonprefetchable memory read transaction
The address is not QUADWORD aligned
The address is near the top of a cache line
A single DWORD read transaction is being performed
A single or two-DWORD memory write transaction is being performed
PI7C8154B is resuming memory write transaction after a target disconnect, and ACK64# was
not asserted by the target in the previous transaction – does not apply when the previous target
termination was a target retry
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MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B