MT46H32M16LFBF-6 AT:C Micron Technology Inc, MT46H32M16LFBF-6 AT:C Datasheet - Page 72

• Manufacturer Part Number: MT46H32M16LFBF-6 AT:C
• Manufacturer: Micron Technology Inc

Specifications of MT46H32M16LFBF-6 AT:C

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 32: Data Input Timing
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. E 6/11 EN
Notes:
Data for any WRITE burst can be truncated by a subsequent PRECHARGE command, as
shown in Figure 42 (page 81) and Figure 43 (page 82). Note that only the data-in
pairs that are registered prior to the
any subsequent data-in should be masked with DM, as shown in Figure 42 (page 81)
and Figure 43 (page 82). After the PRECHARGE command, a subsequent command to
the same bank cannot be issued until
DQS
DM
CK#
DQ
CK
1. WRITE command issued at T0.
2.
3.
4. For x16, LDQS controls the lower byte; UDQS controls the upper byte. For x32, DQS0 con-
5. For x16, LDM controls the lower byte; UDM controls the upper byte. For x32, DM0 con-
4
5
t
t
trols DQ[7:0], DQS1 controls DQ[15:8], DQS2 controls DQ[23:16], and DQS3 controls
DQ[31:24].
trols DQ[7:0], DM1 controls DQ[15:8], DM2 controls DQ[23:16], and DM3 controls
DQ[31:24].
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
t
WPRES
T0
t
1
DQSS
t DS
T1
D
b
IN
t
WPRE
t
DSH
t DH
72
T1n
2
t
Transitioning Data
t
DQSL
DSS
512Mb: x16, x32 Mobile LPDDR SDRAM
t
WR period are written to the internal array, and
3
t
T2
t
RP is met.
t
DQSS (MAX).
DQSS (MIN).
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
DQSH
DSH
T2n
2
t
t
WPST
DSS
3
T3
Don’t Care
© 2009 Micron Technology, Inc. All rights reserved.
WRITE Operation