MT46H32M16LFBF-6 AT:C Micron Technology Inc, MT46H32M16LFBF-6 AT:C Datasheet - Page 29

• Manufacturer Part Number: MT46H32M16LFBF-6 AT:C
• Manufacturer: Micron Technology Inc

Specifications of MT46H32M16LFBF-6 AT:C

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. E 6/11 EN
10. Clock frequency change is only permitted during clock stop, power-down, or self refresh
11. In cases where the device is in self refresh mode for
12.
13. Referenced to each output group: for x16, LDQS with DQ[7:0]; and UDQS with DQ[15:8].
14. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/
15. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and ad-
16. These parameters guarantee device timing but are not tested on each device.
17. The valid data window is derived by achieving other specifications:
18.
19.
20.
21. Fast command/address input slew rate ≥1 V/ns. Slow command/address input slew rate
22. READs and WRITEs with auto precharge must not be issued until
5. The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point
6. A CK and CK# input slew rate ≥1 V/ns (2 V/ns if measured differentially) is assumed for
7. All AC timings assume an input slew rate of 1 V/ns.
8. CAS latency definition: with CL = 2, the first data element is valid at (
9. Timing tests may use a V
tion tools for system design validation is suggested.
at which CK and CK# cross; the input reference voltage level for signals other than CK/
CK# is V
all parameters.
clock at which the READ command was registered; for CL = 3, the first data element is
valid at (2 ×
timing is still referenced to V
ing reference voltage level is V
mode.
of the clock and ends when CKE transitions HIGH.
t
next highest integer.
For x32, DQS0 with DQ[7:0]; DQS1 with DQ[15:8]; DQS2 with DQ[23:16]; and DQS3 with
DQ[31:24].
DQS slew rate is less than 1.0 V/ns, timing must be derated: 50ps must be added to
and
tionality is uncertain.
dresses) are measured between V
V
and
duty cycle and a practical data valid window can be derived. The clock is provided a max-
imum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a
45/55 ratio.
t
CK# inputs, collectively.
t
These parameters are not referenced to a specific voltage level, but specify when the
device output is no longer driving (
t
≥0.5 V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated:
tional 50ps per each 100 mV/ns reduction in slew rate from the 0.5 V/ns.
added, therefore, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is
uncertain.
fied prior to the internal PRECHARGE command being issued.
DAL = (
HP (MIN) is the lesser of
HZ and
HZ (MAX) will prevail over
IL(AC)
I/O
t
t
Full drive strength
DH for each 100 mV/ns reduction in slew rate. If the slew rate exceeds 4 V/ns, func-
QH (
for falling input signals.
DDQ/2
t
t
WR/
LZ transitions occur in the same access time windows as valid data transitions.
t
HP -
50
t
t
.
CK +
CK) + (
Electrical Specifications – AC Operating Conditions
t
QHS). The data valid window derates directly proportional with the clock
t
AC) after the first clock at which the READ command was registered.
t
RP/
20pF
t
CK): for each term, if not already an integer, round up to the
IL
t
CL (MIN) and
-to-V
29
t
DQSCK (MAX) +
DDQ/2
I/O
IH
DDQ/2
512Mb: x16, x32 Mobile LPDDR SDRAM
swing of up to 1.5V in the test environment, but input
IL(DC)
Half drive strength
or to the crossing point for CK/CK#. The output tim-
t
.
HZ) or begins driving (
Micron Technology, Inc. reserves the right to change products or specifications without notice.
to V
t
CH (MIN) actually applied to the device CK and
50
IH(AC)
t
RPST (MAX) condition.
for rising input signals and V
10pF
t
CKE,
t
t
CKE starts at the rising edge
LZ).
© 2009 Micron Technology, Inc. All rights reserved.
t
RAS (MIN) can be satis-
t
HP (
t
CK +
t
IS has an addi-
t
t
CK/2),
IH has 0ps
t
AC) after the
IH(DC)
t
DQSQ,
to
t
DS