MT46H32M16LFBF-6 AT:C Micron Technology Inc, MT46H32M16LFBF-6 AT:C Datasheet - Page 23

• Manufacturer Part Number: MT46H32M16LFBF-6 AT:C
• Manufacturer: Micron Technology Inc

Specifications of MT46H32M16LFBF-6 AT:C

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 10: I
Notes 1–5 apply to all the parameters/conditions in this table; V
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. E 6/11 EN
Parameter/Condition
Operating 1 bank active precharge current:
t
CS is HIGH between valid commands; Address
inputs are switching every 2 clock cycles; Data
bus inputs are stable
Precharge power-down standby current: All banks idle; CKE is
LOW; CS is HIGH;
are switching; Data bus inputs are stable
Precharge power-down standby current: Clock stopped; All
banks idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Ad-
dress and control inputs are switching; Data bus inputs are stable
Precharge nonpower-down standby current: All banks idle; CKE
= HIGH; CS = HIGH;
are switching; Data bus inputs are stable
Precharge nonpower-down standby current: Clock stopped; All
banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Ad-
dress and control inputs are switching; Data bus inputs are stable
Active power-down standby current: 1 bank active; CKE = LOW;
CS = HIGH;
switching; Data bus inputs are stable
Active power-down standby current: Clock stopped; 1 bank ac-
tive; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address
and control inputs are switching; Data bus inputs are stable
Active nonpower-down standby: 1 bank active; CKE = HIGH; CS
= HIGH;
ing; Data bus inputs are stable
Active nonpower-down standby: Clock stopped; 1 bank active;
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Operating burst read: 1 bank active; BL = 4; CL = 3;
(MIN); Continuous READ bursts; Iout = 0mA; Address inputs are
switching every 2 clock cycles; 50% data changing each burst
Operating burst write: One bank active; BL = 4;
(MIN); Continuous WRITE bursts; Address inputs are switching;
50% data changing each burst
Auto refresh: Burst refresh; CKE = HIGH; Ad-
dress and control inputs are switching; Data
bus inputs are stable
Deep power-down current: Address and control pins are stable;
Data bus inputs are stable
RC =
t
RC (MIN);
t
CK =
t
CK =
DD
t
CK (MIN); Address and control inputs are switch-
Specifications and Conditions, –40°C to +105°C (x32)
t
CK =
t
t
CK (MIN); Address and control inputs are
CK =
t
CK =
t
CK (MIN); CKE is HIGH;
t
CK (MIN); Address and control inputs
t
CK (MIN); Address and control inputs
t
JEDEC-standard
option
Reduced page
size option
t
t
CK =
RFC = 138ns
RFC =
t
CK =
t
CK
t
REFI
t
CK
23
Electrical Specifications – I
DD
512Mb: x16, x32 Mobile LPDDR SDRAM
Symbol
/V
I
I
I
I
I
I
I
I
I
DD2NS
I
DD3NS
I
DD2PS
DD3PS
DD4W
DDQ
I
I
DD2N
DD3N
I
DD5A
I
DD2P
DD3P
DD4R
DD0
DD0
DD5
DD8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
= 1.70–1.95V
600
600
115
115
70
70
16
16
95
15
-5
9
4
3
9
8
600
600
110
110
-54
65
65
16
16
95
15
9
4
3
9
8
Max
600
600
105
105
60
60
16
16
95
15
-6
© 2009 Micron Technology, Inc. All rights reserved.
9
4
3
9
8
DD
600
600
100
100
-75
50
50
13
16
95
15
9
4
3
9
8
Parameters
Unit Notes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
10, 11
7, 13
7, 8
10
6
6
7
9
9
8
6
6
6
6