W83627EG Nuvoton Technology Corporation of America, W83627EG Datasheet - Page 208

• Manufacturer Part Number: W83627EG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627EG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CR 27h. (Reserved)
CR 28h. (Global Option; Default 50h)
CR 29h. (OVT#/SMI#, UART A, Game port & MIDI pin select; Default 04h)
7~5
2~0
BIT
BIT
1
0
4
3
Reserved.
READ / WRITE
READ / WRITE
R / W
R / W
R / W
R / W
R / W
DSUALGRQ =>
= 0 Enable UART A legacy mode on IRQ selection, then HCR register
(base
= 1 Disable UART A legacy mode on IRQ selection, then HCR register
(base address + 4) bit 3 is not effective on selecting IRQ.
DSUBLGRQ =>
= 0 Enable UART B legacy mode on IRQ selection, then HCR register
(base
= 1 Disable UART B legacy mode on IRQ selection, then HCR register
(base address + 4) bit 3 is not effective on selecting IRQ.
Select to enable/disable decoding of BIOS ROM range 000E xxxxh.
= 0
= 1
Select to enable/disable decoding of BIOS ROM range FFFE xxxxh.
= 0
= 1
PRTMODS2 ~ 0 =>
= 0xx
= 1xx
address + 4) bit 3 is effective on selecting IRQ.
address + 4) bit 3 is effective on selecting IRQ.
Parallel Port Mode.
Reserved.
Enable decoding of BIOS ROM range at 000E xxxxh.
Disable decoding of BIOS ROM range at 000E xxxxh.
Enable decoding of BIOS ROM range at FFFE xxxxh.
Disable decoding of BIOS ROM range at FFFE xxxxh.
W83627EHF/EF, W83627EHG/EG
-197-
DESCRIPTION
DESCRIPTION
Publication Release Date: April 7, 2009
Version 1.94