W83627EG Nuvoton Technology Corporation of America, W83627EG Datasheet - Page 150

• Manufacturer Part Number: W83627EG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627EG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC and reduced write-current control.
00
01
10
11
The 2 MB/S data rate for the tape drive is only supported by setting DRATE1 and DRATE0 to 01, as
well as setting DRT1 and DRT0 (CRF4 and CRF5 for logical device 0) to 10. Please see the functional
description of CRF4 or CRF5 and the data rate table for individual data-rate settings.
8.2.7
The FIFO register consists of four status registers in a stack, and only one register is presented to the
data bus at a time. The FIFO register stores data, commands, and parameters, and it provides
disk-drive status information. In addition, data bytes pass through the data register to program or obtain
results after a command. In the W83627EHF/EHG/EF/EG, this register is disabled after reset. The
FIFO can enable it and change its values through the configure command.
Status Register 0 (ST0)
500 KB/S (MFM), 250 KB/S (FM), RWC# = 1
300 KB/S (MFM), 150 KB/S (FM), RWC# = 0
250 KB/S (MFM), 125 KB/S (FM), RWC# = 0
1 MB/S (MFM), Illegal (FM), RWC# = 1
2
FIFO Register (R/W base address + 5)
1
1
PRECOMP
DATA RATE
250 KB/S
300 KB/S
500 KB/S
1 MB/S
2 MB/S
1
1
1
0
0
1
0.00 ns (disabled)
250K - 1 Mbps
250.00 ns
DEFAULT PRECOMPENSATION DELAYS
W83627EHF/EF, W83627EHG/EG
-139-
PRECOMPENSATION DELAY
41.67ns
20.8 ns
125 ns
125 ns
125 ns
Publication Release Date: April 7, 2009
2 Mbps Tape drive
0.00 ns (disabled)
125.00 ns
Version 1.94