W83627EG Nuvoton Technology Corporation of America, W83627EG Datasheet
W83627EG
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W83627EHF/EF W83627EHG/EG NUVOTON LPC I/O Note: This document is both for UBC and UBH version except the specified descriptions Date: April 2009 Revision: 1.94 ...
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TABLE OF CONTENTS- 1. GENERAL DESCRIPTION ......................................................................................................... 1 2. FEATURES ................................................................................................................................. 3 3. BLOCK DIAGRAM ...................................................................................................................... 7 4. PIN CONFIGURATION ............................................................................................................... 9 5. PIN DESCRIPTION................................................................................................................... 11 5.1 LPC Interface ...................................................................................................................... 11 5.2 FDC Interface...................................................................................................................... 12 5.3 Multi-Mode Parallel Port...................................................................................................... 14 ...
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Software Programming Example......................................................................................31 7. HARDWARE MONITOR ........................................................................................................... 33 7.1 General Description ............................................................................................................ 33 7.2 Access Interface ................................................................................................................. 34 7.2.1 LPC interface ...................................................................................................................34 2 7.2 interface .....................................................................................................................35 2 7.2.2.1. Serial bus (I C) access timing ............................................................................................................ 36 7.3 ...
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OVT# interrupt mode .......................................................................................................... 58 7.9 Registers and RAM............................................................................................................. 59 7.9.1 Address Port (Port x5h)....................................................................................................59 7.9.2 Data Port (Port x6h) .........................................................................................................59 7.9.3 SYSFANOUT PWM Output Frequency Configuration Register - Index 00h (Bank 0) ......60 7.9.4 SYSFANOUT Output Value Select ...
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AUXFANOUT Start-up Value Register - Index 16h (Bank 0) ...........................................76 7.9.26 AUXFANOUT Stop Time Register - Index 17h (Bank 0) ..................................................77 7.9.27 OVT# Configuration Register - Index 18h (Bank 0)..........................................................77 7.9.28 Reserved - Index 19h-1Fh (Bank 0) .................................................................................78 Value ...
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CPUFANOUT1 Output Value Select Register - Index 61h (Bank 0) ................................95 7.9.56 FAN Configuration Register III - Index 62h (Bank 0) ........................................................95 7.9.57 Target Temperature Register/ CPUFANIN1 Target Speed Register - Index 63h (Bank 0) 96 7.9.58 CPUFANOUT1 Stop ...
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Interrupt Status Register 3 - Index 50h (Bank 4) ............................................................107 7.9.80 SMI# Mask Register 4 - Index 51h (Bank 4) ..................................................................107 7.9.81 Reserved Register - Index 52h (Bank 4) ........................................................................108 7.9.82 BEEP Control Register 3 - Index 53h (Bank ...
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Configuration Control Register (CC Register) (Write base address + 7)........................142 9. UART PORT ........................................................................................................................... 144 9.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)................................. 144 9.2 Register Description.......................................................................................................... 144 9.2.1 UART Control Register (UCR) (Read/Write) ..................................................................144 9.2.2 UART Status Register ...
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Device Control Register (DCR) ......................................................................................167 10.3.5 CFIFO (Parallel Port Data FIFO) Mode = 010................................................................168 10.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011.....................................................................168 10.3.7 TFIFO (Test FIFO Mode) Mode = 110 ...........................................................................168 10.3.8 CNFGA (Configuration Register A) Mode = 111 ...
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WATCHDOG TIMER............................................................................................................... 190 15. VID INPUTS AND OUTPUTS ................................................................................................. 191 15.1 VID Input Detection........................................................................................................... 191 15.2 VID Output Control............................................................................................................ 191 16. PCI RESET BUFFERS ........................................................................................................... 192 17. CONFIGURATION REGISTER............................................................................................... 193 17.1 Chip (Global) Control Register.......................................................................................... 193 17.2 Logical Device ...
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Parallel Port Timing .......................................................................................................................... 256 18.3.7.2. EPP Data or Address Read Cycle Timing Parameters .................................................................... 256 18.3.7.3. EPP Data or Address Read Cycle (EPP Version 1.9)...................................................................... 258 18.3.7.4. EPP Data or Address Read Cycle (EPP Version 1.7)...................................................................... 259 18.3.7.5. ...
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GENERAL DESCRIPTION W83627EHF/EHG/EF/ evolving product from Nuvoton's most popular I/O family. feature a whole new interface, namely LPC (Low Pin Count) interface, which will be supported in the new generation chip-set. This interface as its name suggests ...
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Moreover, W83627EHF/EHG supports the Smart Fan control system, including the TM “Thermal Cruise ” and “Speed Cruise friendly. W83627EHF/EHG/EF/EG is made to fully ...
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FEATURES General • Meet LPC Spec. 1.01 • Support LDRQ#(LPC DMA), SERIRQ (Serial IRQ) • Integrated Hardware Monitor functions © • Compliant with Microsoft PC98/PC99/PC2001 System Design Guide • Support DPM (Device Power Management), ACPI • Programmable configuration settings ...
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Completely compatible with industry standard 82077 • 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate • Support 3-mode FDD, and its Windows driver UART • Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs • MIDI ...
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Enhanced printer port back-drive current protection Game Port • Support two separate Joysticks • Support every Joystick two axis (X, Y) and two button (A, B) controllers MIDI Port • The baud rate is 31.25 K baud • 16-byte ...
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GPIO port 1 and 4 can not only serve as simple I/O ports but also watch dog timer output, Power LED output, Suspend LED output • Functional in power down mode (GP24 ~ GP27, GPIO-3, GPIO-4, GPIO-5) OnNow Functions ...
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PQFP 3. BLOCK DIAGRAM LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ Game Joystick interface Port signals MSI MIDI MSO General-purpose GPIO I/O pins Keyboard/Mouse KBC data and clock W83627EHF/EF, W83627EHG/EG LPC Interface FDC URA PRT ACPI W83627EF/EG ...
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LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ Joystick interface Game signals Port MSI MIDI MSO General-purpose I/O pins GPIO Hardware monitor HM channel and Vref Keyboard/Mouse KBC data and clock W83627EHF/EF, W83627EHG/EG LPC Interface FDC URA PRT ACPI W83627EHF/EHG ...
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PIN CONFIGURATION AVCC AVCC 103 103 CPUTIN CPUTIN 104 104 SYSTIN SYSTIN 105 105 VID5 VID5 VID4 VID4 106 106 107 107 VID3 VID3 108 108 VID2 VID2 VID1 VID1 109 109 110 110 VID0 VID0 111 111 AUXFANIN0 ...
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W83627EHF/EF, W83627EHG/EG 3VCC 3VCC 3VCC 3VCC 3VCC 3VSB 3VSB 3VSB 3VSB 3VSB 103 103 103 103 103 104 104 104 104 104 105 105 105 105 105 NC ...
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PIN DESCRIPTION Note: Please refer to Section 18.2 DC CHARACTERISTICS for details. AOUT - Analog output pin AIN - Analog input pin IN - CMOS level Schmitt-triggered input pin TTL level input pin ...
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SYMBOL PIN I/O IN PCICLK 21 t OUT LDRQ SERIRQ 23 I/O 12t I/O LAD[3:0] 24-27 12t IN LFRAME LRESET 5.2 FDC Interface SYMBOL PIN I/O DRVDEN0 1 OD Drive Density Select bit ...
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SYMBOL PIN I/O Write data. This logic low open drain writes pre-compensation serial data OD WD the selected FDD. An open drain output. OD WE# 11 Write enable. An open drain output. 24 Track 0. This Schmitt-triggered ...
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Multi-Mode Parallel Port SYMBOL PIN I/O PRINTER MODE: An active high input on this pin indicates that the printer is IN SLCT 31 ts selected. Refer to the description of the parallel port for definition of this pin in ...
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SYMBOL PIN I/O PRINTER MODE: INIT Output line for the printer initialization. Refer to the description of INIT# 44 OUT the parallel port for the definition of this pin in ECP and EPP / 12 mode. PRINTER MODE: ...
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SYMBOL PIN I/O PRINTER MODE: PD5 I/O PD5 37 Parallel port data bus bit 5. 12ts parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD6 I/O PD6 36 Parallel port data bus bit ...
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SYMBOL PIN I/O Data Set Ready. An active low signal indicates the modem or IN DSRB# data set is ready to establish a communication link and transfer t 79 data to the UART. I/OD GP46* General purpose I/O port 4 ...
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SYMBOL PIN I/O IRRX IR Receiver input. I/OD GP43*** General purpose I/O port 4 bit 3. 12 UART A Serial Output used to transmit serial data out to the OUT SOUTA 8 communication link. During power on reset, ...
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Note. The * sign see 5.10.8 GPIO-1 and GPIO-4 with WDTO# / SUSLED / PLED multi-function 5.5 KBC Interface SYMBOL PIN I/O GA20M 59 OUT 12 KBRST# 60 OUT 12 KCLK I/OD 16ts 62 GP27 I/OD 16t KDAT I/OD 16ts ...
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SYMBOL PIN I/O VIN3 96 AIN 0V to 2.048V FSR Analog Inputs. VIN2 97 AIN 0V to 2.048V FSR Analog Inputs. VIN1 98 AIN 0V to 2.048V FSR Analog Inputs. VIN0 99 AIN 0V to 2.048V FSR Analog Inputs. CPUVCORE ...
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SYMBOL PIN I/O CPUFANIN0 112 SYSFANIN 113 CPUFANIN1 I/O 12ts IN 119 MSI ts GP21 I/OD 12ts AUXFANOUT 7 CPUFANOUT0 115 AOUT SYSFANOUT 116 AOUT/ CPUFANOUT1 OUT 12t 120 MSO OUT 12t GP20 I/OD 12t 5.7 Game Port ...
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SYMBOL PIN I/O GPX1 I/OD 126 12ts GP12* GPX2 I/OD 125 12ts GP13** GPY2 I/OD 124 12ts GP14* GPY1 I/OD 123 12ts GP15** IN GPSB2 ts 122 I/OD GP16* 12ts IN GPSA2 ts 121 I/OD GP17** 12ts IN MSI ts ...
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SYMBOL PIN I/O AOUT/ CPUFANOUT1 OUT 12t GP20 I/OD 12t Note. The * sign see 5.10.8 GPIO-1 and GPIO-4 with WDTO# / SUSLED / PLED multi-function 5.8 ACPI Interface SYMBOL PIN I/O PSIN GP56 I/OD 12t PSOUT# ...
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SYMBOL PIN I/O GP34 I/OD 12t 5.9 General Purpose I/O Port 5.9.1 GPIO Power Source SYMBOL POWER SOURCE GPIO port 1 3VCC GPIO port 2 (Bit0-3) 3VCC GPIO port 2 (Bit4-7) 3VSB GPIO port 3 3VSB GPIO port 4 3VSB ...
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SYMBOL PIN I/O IN MSI ts GP22 19 I/OD 12t GP23 2 I/OD 12t GP24 I/OD 16t 66 MDAT I/OD 16ts GP25 I/OD 16t 65 MCLK I/OD 16ts GP26 I/OD 16t 63 KDAT I/OD 16ts GP27 I/OD 16t 62 KCLK ...
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SYMBOL PIN I/O GP34 I/OD General purpose I/O port 3 bit 4. 12t 88 RSTOUT4# OUT Secondary LRESET# output 4. 12 GP35 87 I/OD General purpose I/O port 3 bit 5 12t GP36 69 I/OD General purpose I/O port 3 ...
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SYMBOL PIN I/O General purpose I/O port 5 bit 5. GP55 I/O 12t mode) 70 SUSLED OUT Suspended LED output. 12 GP56 I/OD General purpose I/O port 5 bit 6. 12t 68 Panel Switch Input. This pin is high active ...
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Analog +3.3V power input. Internally supplier to all analog AVCC 114 circuitry. Internally connected to all analog circuitry. The ground reference AGND 117 for all analog inputs. GND 20,55 Ground. W83627EHF/EF, W83627EHG/ ...
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CONFIGURATION REGISTER ACCESS PROTOCOL The W83627EHF/EHG/EF/EG uses Super I/O protocol to access configuration registers to set up different types of configurations. The W83627EHF/EHG/EF/EG has totally twelve Logical Devices (from Logical Device 0 to Logical Device B with the exception ...
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LOGICAL DEVICE NUMBER GPIO1, GPIO 6, Game Port & MIDI port 6.1 Configuration Sequence Power-on Reset Power-on Reset Power-on Reset Power-on Reset Wait for key string Wait for key string Wait ...
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To program the W83627EHF/EHG/EF/EG configuration registers, the following configuration procedures must be followed in sequence: (1). Enter the Extended Function Mode. (2). Configure the configuration registers. (3). Exit the Extended Function Mode. 6.1.1 Enter the Extended Function Mode To place ...
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OUT DX, AL ;----------------------------------------------------------------------------- ; Configure Logical Device 1, Configuration Register CRF0 ;----------------------------------------------------------------------------- MOV DX, 2EH MOV AL, 07H OUT DX point to Logical Device Number Reg. MOV DX, 2FH MOV AL, 01H OUT DX select ...
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INDEX R/W 28h R/W 29h R/W 2Ah R/W 2Bh 2Ch R/W 2Dh R/W 2Eh R/W 2Fh R/W S: Strapping; x: chip version. 7. HARDWARE MONITOR 7.1 General Description The W83627EHF/EHG can be used to monitor several critical hardware parameters of ...
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An optional beep tone could be used as warning signals when the monitored parameters are out of the preset range. 7.2 Access Interface W83627EHF/EHG provides two interface for microprocessor to read/write hardware monitor internal registers. 7.2.1 LPC interface The first ...
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LPC Bus Port 5h Index Register Port 6h Data Register Figure 7.1 : LPC interface access diagram 2 7.2 interface 2 The second interface uses I C Serial Bus. W83627EHF/EHG has a programmable serial bus address. It defined ...
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Serial bus (I C) access timing (a) Serial bus write to internal address register followed by the data byte 0 SCL SDA Start By Master Frame 1 Serial Bus Address Byte SCL ...
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CPUVCORE R1 V0 Positive Voltage Input VIN2 VIN3 VIN4 V1 Negative Voltage Input R THM 10K@25 C, beta=3435K 7.3.1 Monitor over 2.048V voltage The +12V input voltage can be expressed as following equation. The value of R1 and R2 can ...
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Both of pin 12 and pin 114 are connected to the power supply VCC with +3.3V. There are two functions in these 2 pins with 3.3V. The first function is to supply internal (digital/analog) power in the W83627EHF/EHG and the ...
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TEMPERATURE 8-BIT DIGITAL OUTPUT 8-BIT BINARY -0.5°C - -1°C 1111,1111 -25°C 1110,0111 -55°C 1100,1001 7.3.3.1. Monitor temperature from thermistor The W83627EHF/EHG can connect three thermistors to measure three different environment temperature. The specification of thermistor should be considered to (1) ...
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FAN Speed Count and FAN Speed Control 7.4.1 Fan speed count Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can not ...
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Nominal Divisor RPM 128 68 7.4.2 Fan speed control W83627EHF/EHG provides two controllable methods for Fan speed control. One is PWM duty cycle output and the other is DC voltage output. Either PWM or DC output can be programmed at ...
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The monitor time of the 3 temperature sets 0.044mS = 3.168 ms The 10 voltage sets 0.044 ms = 7.04 ms Total conversion time = 3.168 + 7.04 = 10.208 ms Please note ...
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Smart Fan Control TM SMART FAN I： Smart Fan Control provides two mechanisms. One is Thermal Cruise mode and the other is Fan Speed Cruise mode. When enable Smart Fan, the Fan output will start from previous setting of ...
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If the temperature still exceeds the high limit (ex: 58°C), Fan output will increase slowly. If the fan has been operating in its fully speed but the temperature still exceeds the high limit(ex: 58°C), a warning message will be ...
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One more protection is provided that Fan output will not be decreased the above (3) situation in order to keep the fans running with a minimum speed. By setting Bank0 Index12h.bit3 Fan output will ...
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A Count 170 160 150 (%) 100 Fan output 50 0 7.6.3 Manual Control Mode Smart Fan control system can be disabled and the fan speed control algorithm can be programmed by BIOS or application software. The programming method must ...
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REGISTER DESCRIPTION ADDRESS Output Value Current Bank0 AUXFANOUT 11h Output Value Current Bank0 CPUFANOUT1 61h Output Value Table 7.3-2 Relative Register-at Thermal Cruise Mode of Smart Fan I control mode THERMAL- TARGET TOLERANCE CRUISE MODE TEMPERATURE SYSFANOUT CR[05h] CR[07h] Bit0-3 ...
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SYSFANOUT CR[05h] CPUFANOUT0 CR[06h] AUXFANOUT CR[13h] CPUFANOUT1 CR[63h] TM SMART FAN III Concept TM SMART FAN III mode sets a target temperature through BIOS or application software and W83627EHF/EHG controls the fan speed so that the temperature could meet the ...
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Figure 7.9 shows the initial condition of SMART FAN Tolerance, Maximum Fan Output and Minimum Fan Output must be set first. If the currently measured temperature is within the (Target Temperature ± Temperature Tolerance), the fan speed remains constant. ...
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The fan-slow-down and Target Temperature comparison-then-shift process continue until currently measured temperature locates within (Target Temperature X ± Temperature Tolerance), or fan output speed hits its minimum speed. (11) Please be noted that “Speed-down Slope” shown in the Figure ...
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Current Temp. > Target Temp. + Tol. Current Temp. > Target Temp. + Tol. Fan output Fan output (DC / PWM) (DC / PWM) Max. Fan Output Max. Fan Output Fan Initial Fan Initial Output Value Output Value Min. Fan ...
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TM Smart Fan III control system can be disabled and the fan speed control algorithm can be programmed by BIOS or application software. The programming method must be set fan configuration at bank 0 index 04h,bit5-4,index 12h bit2~1 index 62h ...
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TM Smart Fan III Output Step Mode CPUFANOUT0 CR[68h] CPUFANOUT1 CR[6Ah] W83627EHF/EF, W83627EHG/EG Step Down Step Up Keep Min. Fan Time Time Output value CR[0Eh] CR[0Fh] CR[12h] bit 4 CR[0Eh] CR[0Fh] CR[12h] bit 6 Publication Release Date: April 7, 2009 ...
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SMI# interrupt mode The SMI#/OVT# pin is a multi-function pin. The function is selected at Configuration Register CR[29h] bit 6. 7.7.1 Voltage SMI# mode SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below ...
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Temperature SMI# mode 7.7.3.1. Temperature sensor 1(SYSTIN) SMI# interrupt has 3 modes (1) Comparator Interrupt Mode Setting the T (Temperature Hysteresis) limit to 127°C will set temperature sensor 1 SMI# to the HYST Comparator Interrupt Mode. Temperature exceeds T ...
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T HYST 127 SMI *Interrupt Reset when Interrupt Status Registers are read Figure 7. HYST SMI# *Interrupt Reset when Interrupt Status Registers are read W83627EHF/EF, W83627EHG/ HYST SMI# * ...
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Temperature sensor 2(CPUTIN) and sensor 3(AUXTIN) SMI# interrupt has two modes It is programmed at Bank0 Index 4Ch.bit 6. (1) Comparator Interrupt Mode Temperature exceeding T causes an interrupt and this interrupt will be reset by reading all the ...
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OVT# interrupt mode The SMI#/OVT# pin (pin multi-function pin. The function is selected at Configuration Register CR[29h] bit 6. The OVT# mode selection bits are at Bank0 Index18h bit4, Bank1 Index 52h bit1 and Bank2 Index ...
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Registers and RAM Address Port and Data Port are set in the register CR60 and CR61 of Device B which is Hardware Monitor Device. The value in CR60 is high byte and that in CR61 is low byte. For ...
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Bit 7-0: Data to be read from written to RAM and Register. 7.9.3 SYSFANOUT PWM Output Frequency Configuration Register - Index 00h (Bank 0) Register Location: 00h Power on Default Value: 04h Attribute: Read/Write Size: ...
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PWM output frequency 7.9.4 SYSFANOUT Output Value Select Register - Index 01h (Bank 0) Register Location: 01h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits (1)If SYSFANOUT be programmed as PWM ...
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BIT BIT BIT BIT BIT BIT ...
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BIT BIT BIT BIT BIT BIT ...
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PWM output frequency = 7.9.6 CPUFANOUT0 Output Value Select Register - Index 03h (Bank 0) Register Location: 03h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits (1)If CPUFANOUT0 be programmed ...
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Bit 7-6: Reserved Bit 5-4: CPUFANOUT0 mode control. Set 00, CPUFANOUT0 is as Manual Mode. (Default). Set 01, CPUFANOUT0 is as Thermal Cruise Mode. Set 10, CPUFANOUT0 is as Fan Speed Cruise Mode. Set 11, CPUFANOUT0 is ...
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Thermal Cruise mode: Bit 7: Reserved. Bit 6-0: SYSTIN Target Temperature. (2)When at Fan Speed Cruise mode: Bit 7-0: SYSFANIN Target Speed. 7.9.9 CPUTIN Target Temperature Register/ CPUFANIN0 Target Speed Register - Index ...
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Power on Default Value: 00h Attribute: Read/Write Size: 8 bits (1)When at Thermal Cruise mode or Bit 7-4: Tolerance of CPUTIN Target Temperature. Bit 3-0: Tolerance of SYSTIN Target Temperature. (2)When at Fan Speed ...
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Please note that Stop Value does not mean that fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimam value, and this is Stop Value. ...
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When at Thermal Cruise mode, SYSFANOUT value will increase from 0 to this register value to provide a minimum value to turn on the fan. 7.9.14 CPUFANOUT0 Start-up Value Register - Index 0Bh (Bank 0) Register ...
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When at Thermal Cruise mode, this register determines the time of which SYSFANOUT value is from stop value to 0. (1)When at PWM output: The unit of this register is 0.1 second. The default time is ...
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Fan Output Step Down Time Register - Index 0Eh (Bank 0) Register Location: 0Eh Power on Default Value: 0Ah Attribute: Read/Write Size: 8 bits This register determines the speed of FANOUT decreasing its value ...
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This register determines the speed of FANOUT increasing the its value in Smart Fan Control mode. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 1 seconds. (2)When at DC Voltage output: The ...
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PWM output frequency = the formula is 7.9.20 AUXFANOUT Output Value Select Register - Index 11h (Bank 0) Register Location: 11h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits (1)If AUXFANOUT be programmed as ...
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Bit 7: Reserved Bit 6: Set 1, CPUFANOUT1 value will decrease to and keep the value set in Index 64h when temperature goes below target range. This is to maintain the fan speed in a minimum ...
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Attribute: Read/Write Size: 8 bits (1)When at Thermal Cruise mode: Bit 7: Reserved. Bit 6-0: AUXTIN Target Temperature. (2)When at Fan Speed Cruise mode: Bit 7-0: AUXFANIN0 Target Speed. 7.9.23 Tolerance of Target Temperature ...
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Bit 3-0: Tolerance of AUXFANIN0 Target Speed. 7.9.24 AUXFANOUT Stop Value Register - Index 15h (Bank 0) Register Location: 15h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits When at Thermal Cruise mode, AUXFANOUT ...
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When at Thermal Cruise mode, AUXFANOUT value will increase from 0 to this register value to provide a minimum value to turn on the fan. 7.9.26 AUXFANOUT Stop Time Register - Index 17h (Bank 0) ...
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Attribute: Read/Write Size: 8 bits 7 6 Bit 7: Reserved. Bit 6: Set to 1, disable temperature sensor SYSTIN over-temperature (OVT#) output. Set to 0, enable the SYSTIN OVT# output. Bit 5: Reserved. Bit 4: SYSTIN OVT# mode select. This ...
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ADDRESS A6-A0 28h SYSFANIN reading Note: This location stores the number of counts of the internal clock per revolution. 29h CPUFANIN0 reading Note: This location stores the number of counts of the internal clock per revolution. 2Ah AUXFANIN0 reading Note: ...
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ADDRESS A6-A0 39h SYSTIN temperature sensor High Limit 3Ah SYSTIN temperature sensor Hysteresis Limit 3Bh SYSFANIN Fan Count Limit Note the number of counts of the internal clock for the Low Limit of the fan speed. 3Ch CPUFANIN0 ...
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Bit 7: A one restores power on default value to some registers. This bit clears itself since the power on default is zero. Bit 6: Reserved Bit 5: Reserved Bit 4: Reserved Bit 3: A ...
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Bit 6: A one indicates the fan count limit of SYSFANIN has been exceeded. Bit 5: A one indicates a High limit of CPUTIN temperature has been exceeded. Bit 4: A one indicates a High limit of SYSTIN temperature has ...
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Attribute: Read/Write Size: 8 bits Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt. 7.9.34 SMI# Mask Register 2 - Index 44h (Bank 0) Register Location: 44h Power on Default Value: FFh Attribute: ...
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Bit 7: CASEOPEN Clear Control. Write 1 to this bit will clear CASEOPEN status. This bit won’t be self cleared, please write 0 after event be cleared. The function is as same as LDA, CR[E6h] bit 5. Bit 6-3: ...
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Bit 0: AUXFANIN1 Input Control. Set to 1, pin58 (AUXFANIN1) acts as FAN tachometer input, which is default value. Set to 0, this pin58 acts as FAN control signal and the output value of FAN control is set by this ...
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Bit 7-6: Select Temperature source for CPUFANOUT1 at Thermal Cruise mode or S Mode <7:6> – SYSTIN. <7:6> CPUTIN.(Default) <7:6> AUXTIN. <7:6> – Reserved. Bit 5-0: Reserved. 7.9.41 Fan Divisor ...
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Register Location: 4Ch Power on Default Value: 10h Attribute: Read/Write Size: 8 bits Bit 7: CPUFANIN1 Divisor bit2. Bit 6: Set to 1, the SMI# output type of Temperature CPUTIN/AUXTIN is set to Comparator Interrupt mode. Set ...
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Bit 7-6: Reserved. Bit 5: AUXFANIN0 output value if bit 4 sets to 0. Write 1, pin111(AUXFANIN0) always generates a logic high signal. Write 0, pin111 always generates a logic low signal. This bit is default 0. Bit ...
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Bit 7: HBACS - High byte access. Set to 1, access Index 4Fh high byte register. Set to 0, access Index 4Fh low byte register. (default 1) Bit 6: Reserved. This bit should be set to 0. ...
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Bit 15-8: Vendor ID High Byte if Index 4Eh.bit7=1. Default 5Ch. Bit 7-0: Vendor ID Low Byte if Index 4Eh.bit7=0. Default A3h. 7.9.46 Nuvoton Test Register - Index 50h-55h (Bank 0) 7.9.47 BEEP Control Register 1 - Index ...
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Bit 2: BEEP output control for AVCC if the monitor value exceeds the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 1: BEEP output control for VIN0 if the monitor value ...
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Bit 0: BEEP output control for VIN1 if the monitor value exceeds the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. 7.9.49 Chip ID - Index 58h (Bank 0) Register Location: 58h ...
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Bit 1-0: CPUFANIN1 Divisor bit 1:0. 7.9.51 Reserved - Index 5Ah-5Ch (Bank 0) 7.9.52 VBAT Monitor Control Register - Index 5Dh (Bank 0) Register Location: 5Dh Power on Default Value: 00h Attribute: Read/Write Size: 8 bits Bit ...
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BIT 2 BIT 1 BIT 0 FAN DIVISOR 7.9.53 Reserved Register - Index 5Eh-5Fh (Bank 0) 7.9.54 CPUFANOUT1 PWM Output Frequency Configuration Register - Index 60h (Bank 0) Register Location: 60h ...
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PWM output frequency the formula is 7.9.55 CPUFANOUT1 Output Value Select Register - Index 61h (Bank 0) Register Location: 61h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits (1)If CPUFANOUT1 be programmed as PWM ...
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Bit7: Reserved. Bit 6: CPUFANOUT1 output mode selection. Set to 0, CPUFANOUT1 pin is as PWM output duty cycle so that it can drive a logical high or low signal. Set to 1, CPUFANOUT1 pin ...
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Thermal Cruise mode or Bit 7: Reserved. Bit 6-0: Target Temperature of select temperature source. (2)When at Fan Speed Cruise mode: Bit 7-0: CPUFANIN1 Target Speed. 7.9.58 CPUFANOUT1 Stop Value Register - Index ...
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Power on Default Value: 01h Attribute: Read/Write Size: 8 bits When at Thermal Cruise mode, CPUFANOUT1 value will increase from 0 to this register value to provide a minimum value to turn on the fan. ...
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CPUFANOUT0 Maximum Output Value Register - Index 67h (Bank 0) Register Location: 67h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits When at SMART FAN III mode, CPUFANOUT0 value will increase ...
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Attribute: Read/Write Size: 8 bits When at SMART FAN III mode, CPUFANOUT1 value will increase to this value. This register should be written a non-zero value that cannot lower than Stop value. 7.9.64 CPUFANOUT1 Output ...
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Bit 7-0: Temperature <8:1> of CPUTIN sensor, which is high byte, means 1 7.9.66 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1) Register Location: 51h Attribute: Read Only Size: 8 bits 7 ...
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Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# mode select. This ...
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CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1) Register Location: 55h Power on Default Value: 50h Attribute: Read/Write Size: 8 bits Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default ...
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Bit 7: Temperature <8:1> of AUXTIN sensor, which is high byte, means 1 7.9.73 AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2) Register Location: 51h Attribute: Read Only Size: 8 bits 7 6 ...
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Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should ...
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Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. 7.9.77 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2) Register Location: 55h Power on Default Value: 50h Attribute: Read/Write Size: ...
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Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. 7.9.79 Interrupt Status Register 3 - Index 50h (Bank 4) Register Location: 50h Power on Default Value: 00h Attribute: Read Only Size: 8 bits 7 ...
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Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 Bit 7-5: Reserved. Bit 4: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 3-2: Reserved. Bit 1: A one disables the corresponding interrupt status ...
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Bit 1: BEEP output control for VBAT if the monitor value exceeds the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 0: BEEP output control for VSB if the monitor value ...
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AUXTIN Temperature Sensor Offset Register - Index 56h (Bank 4) Register Location: 56h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits Bit 7-0: AUXTIN temperature offset value. The value in this register will be ...
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Bit 6: SYSFANIN status. Read 1, the fan speed count is over the limit value. Read 0, the fan speed count is in the limit range. Bit 5: CPUTIN temperature sensor status. Read 1, the temperature exceeds the over-temperature limit ...
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Bit 5: AUXTIN temperature sensor status. Read 1, the temperature exceeds the over-temperature limit value. Read 0, the temperature is in under the hysteresis value. Bit 4: Case Open status. Read 1, the case open is detected and latched. Read ...
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Bit 3: VIN4 Voltage status. Read 1, the voltage of VIN4 is over/under the limit value. Read 0, the voltage of VIN4 is in the limit range. Bit 2: Smart Fan of AUXFANIN warning status. Read 1, the AUXTIN temperature ...
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ADDRESS A6-A0 Note the number of counts of the internal clock for the Low Limit of the fan speed. 7.9.92 Nuvoton Test Register - Index 50h-57h (Bank 6) W83627EHF/EF, W83627EHG/EG DESCRIPTION - 114 - ...
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FLOPPY DISK CONTROLLER 8.1 FDC Functional Description The floppy disk controller (FDC) of the W83627EHF/EHG/EF/EG integrates all of the logic required for floppy disk control. The FDC implements a FIFO which provides better system performance in multi-master systems, and ...
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Byte 8 Byte 15 Byte At the start of a command, the FIFO is always disabled, and command parameters must be sent based upon the RQM and DIO bit settings in the Main Status Register. When the FDC enters ...
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The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This scheme packs more data bits into the same area. FDCs ...
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DIR = 1: step in DS0: Disk Drive Select 0 DS1: Disk Drive Select 1 DTL: Data Length EC: Enable Count EFIFO: Enable FIFO EIS: Enable Implied Seek EOT: End of Track FIFOTHR: FIFO Threshold GAP: Gap Length Selection GPL: ...
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ST0: Status Register 0 ST1: Status Register 1 ST2: Status Register 2 ST3: Status Register 3 WG: Write gate alters timing of WE (1) Read Data PHASE R Command W MT MFM HDS ...
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Read Deleted Data PHASE R Command W MT MFM HDS DS1 DS0 W ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- ...
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Read A Track D7 D6 PHASE R/W Command W 0 MFM HDS DS1 W ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W ...
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PHASE R Command W 0 MFM HDS DS1 DS0 Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- ...
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Verify PHASE R Command W MT MFM HDS DS1 DS0 W ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- ...
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PHASE R Result (7) Write Data PHASE R Command W MT MFM HDS DS1 DS0 W ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ...
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Write Deleted Data PHASE R Command W MT MFM HDS DS1 DS0 W ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- ...
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Format A Track PHASE R Command W 0 MFM HDS DS1 DS0 W ---------------------- N ------------------------ W --------------------- SC ----------------------- W --------------------- GPL --------------------- W ---------------------- D ------------------------ Execution W ---------------------- C ------------------------ ...
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PHASE R DS1 DS0 Execution (11) Sense Interrupt Status PHASE R Command Result R ---------------- ST0 ------------------------- R ---------------- PCN ------------------------- (12) Specify PHASE R ...
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PHASE R HDS DS1 DS0 W -------------------- NCN ----------------------- Execution R (14) Configure PHASE R Command EIS EFIFO POLL | ------ ...
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PHASE R Command Result R ----------------------- PCN-Drive 0-------------------- R ----------------------- PCN-Drive 1 ------------------- R ----------------------- PCN-Drive 2-------------------- R ----------------------- PCN-Drive 3 ------------------- R --------SRT ------------------ | --------- HUT -------- R ----------- HLT -----------------------------------| ND ...
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Lock PHASE R Command W LOCK Result (19) Sense Drive Status PHASE R Command HDS DS1 DS0 Result R ...
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Register Descriptions There are several status, data, and control registers in the W83627EHF/EHG/EF/EG. These registers are defined below, and the rest of this section provides more details about each one of them. ADDRESS OFFSET base address + 0 base ...
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This bit indicates the complement of the STEP# output. TRAK0#(Bit 4): This bit indicates the value of the TRAK0# input. HEAD (Bit 3): This bit indicates the complement of the HEAD# output. 0 side 0 1 side 1 INDEX#(Bit 2): ...
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DRQ (Bit 6): This bit indicates the value of the DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of the latched STEP# output. TRAK0 (Bit 4): This bit indicates the complement of the TRAK0# input. HEAD# ...
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Drive SEL0 (Bit 5): This bit indicates the status of the DO REGISTER, bit 0 (drive-select bit 0). WDATA Toggle (Bit 4): This bit changes state on every rising edge of the WD# output pin. ...
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RESERVED (Bit 7) RESERVED (Bit 6) DSA# (Bit 5): This bit indicates the status of the DSA# output pin. WD F/F (Bit 4): This bit indicates the complement of the WD# output pin, which is latched on every rising edge ...
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Tape Drive Register (TD Register) (Read base address + 3) This register is used to assign a particular drive number to the tape drive support mode of the data separator. This register also holds ...
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Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the bits in LD0 CRF2. Which two bits are reflected depends on the last drive selection in the DO register. Floppy Boot drive 1, 0 ...
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The Data Rate Register is used to set the transfer rate and write precompensation. However, in PC-AT and PS/2 Model 30 and PS/2 modes, the data rate is controlled by the CC register, not by the DR register ...
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PRECOMP DATA RATE 250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write-current ...
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US1, US0 Drive Select: 00 Drive A selected 01 Reserved 10 Reserved 11 Reserved HD Head address: 1 Head selected 0 Head selected NR Not Ready: 1 Drive is not ready 0 Drive is ...
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Status Register 3 (ST3 8.2.8 Digital Input Register (DI Register) (Read base address + 7) The Digital Input Register is an 8-bit, read-only register used for diagnostic purposes. In PC/XT or PC/AT mode, only bit 7 is ...
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HIGHDENS# (Bit 0): 0 500 KB MB/S data rate (high-density FDD) 1 250 KB/S or 300 KB/S data rate In PS/2 Model 30 mode, the bit definitions are as follows DSKCHG (Bit 7): This bit ...
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Bit 7-2: Reserved. These bits should be set to 0. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR ...
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UART PORT 9.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B) The UARTs are used to convert parallel data into serial format for transmission and to convert serial data into parallel format during reception. The serial data format is a ...
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EPE is logical 0, the parity bit is fixed as logical 1 when transmitting and checking. Bit 4: EPE. When PBE is set to logical 1, this bit counts the number of logical 1's in the data word ...
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Register Address Base Receiver RBR RX Data Buffer BDLAB = 0 Bit 0 Register (Read Only Transmitter TBR TX Data Buffer Register BDLAB = 0 Bit 0 (Write Only Interrupt Control ICR RBR ...
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UART Status USR RBR Data Register Ready (RDR Handshake HSR CTS Status Register Toggling (TCTS User Defined UDR Bit 0 Register + 0 Baudrate BLL Bit 0 Divisor Latch BDLAB = 1 Low + ...
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UART Status Register (USR) (Read/Write) This 8-bit register provides information about the status of data transfer during communication Bit 7: RFEI. In 16450 mode, this bit is always set to logical 0. In 16550 ...
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Bit 1: OER. This bit is set to logical 1 to indicate that the received data have been overwritten by the next received data before they were read by the CPU. In 16550 mode, it indicates the same condition, instead ...
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Handshake Status Register (HSR) (Read/Write) This register reflects the current state of the four input pins used with handshake peripherals such as modems and records changes on these pins Bit 7: This bit is the opposite ...
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UART FIFO Control Register (UFR) (Write only) This register is used to control the FIFO functions of the UART Bit 6, 7: These two bits are used to set the active level of the receiver ...
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Bit 7, 6: These two bits are set to logical 1 when UFR, bit Bit 5, 4: These two bits are always logical 0. Bit 3: In 16450 mode, this bit is logical ...
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ISR Bit Bit Bit Bit Interrupt Interrupt Type priority Fourth Handshake status ** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1. 9.2.7 Interrupt Control Register (ICR) ...
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Programmable Baud Generator (BLL/BHL) (Read/Write) Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to generate a 1.8461 MHz frequency and divide divisor from the baud generator ...
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BAUD RATE FROM DIFFERENT PRE-DIVIDER PRE-DIV: 13 PRE-DIV:1.62 PRE-DIV: 5 1.8461M HZ 14.769M HZ 24M HZ 19200 153600 249600 38400 307200 499200 57600 460800 748800 115200 921600 1497600 ** Unless specified, the error percentage for all of the baud rates ...
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PARALLEL PORT 10.1 Printer Interface Logic The W83627EHF/EHG/EF/EG parallel port can be attached to devices that accept eight bits of parallel data at standard TTL level. The W83627EHF/EHG/EF/EG supports the IBM XT/AT compatible parallel port (SPP), the bi-directional parallel ...
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HOST CONNECTOR W83627EHF/EHG/EF/ 10.2 Enhanced Parallel Port (EPP) The following table lists the registers used in the EPP mode and identifies the bit ...
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Notes: 1. These registers are available in all modes. 2. These registers are available only in EPP mode. REGISTER 7 6 Data ...
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Printer Status Buffer The CPU reads the printer status by reading the printer status buffer. The bit definitions are as follows Bit 7: This signal is active during data entry, when the printer is off-line during printing, ...
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Bit 7, 6: These two bits are always read as logical 1. They can be written. Bit 5: Direction control bit When this bit is logical 1, the parallel port is in input mode (read); when it is logical 0, ...
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When any EPP data port is accessed, the contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP data write cycle to be performed, and the ...
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EPP Pin Descriptions EPP NAME TYPE NWrite O Denotes read or write operation for address or data. PD<0:7> I/O Bi-directional EPP address and data bus. Intr I Used by peripheral device to interrupt the host. NWait I Inactivated to ...
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EPP Version 1.9 Operation The EPP read/write operation can be completed under the following conditions nWait is active low, the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or write cycle (nWrite active low, nDStrb/nAStrb active low) ...
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Extended Capabilities Parallel (ECP) Port This port is software- and hardware-compatible W83627EHF/EHG/EF/EG parallel port may be used in standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in ...
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The next two tables list the registers used in the ECP mode and provide a bit map of the parallel port and ECP registers. NAME ADDRESS data Base+000h ecpAFifo Base+000h dsr Base+001h dcr Base+002h cFifo Base+400h ecpDFifo Base+400h tFifo Base+400h ...
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These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO. Each register (or pair of registers, in some cases) is discussed below. 10.3.2 Data and ecpAFifo Port Modes 000 (SPP) and 001 (PS/2) (Data ...
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Device Status Register (DSR) These bits are logical 0 during a read of the Printer Status Register. The bits of this status register are defined as follows: 7 Bit 7: This bit reflects the complement of the Busy input. ...
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Bit 7, 6: These two bits are always read as logical one and cannot be written. Bit 5: If the mode is 000 or 010, this bit has no effect and the direction is always out. In other modes, 0 ...
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The bit definitions are as follows: 7 Bit 7: This bit is read-only logical 0 during a read, which means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ ...
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Bit 7-5: Read/Write. These bits select the mode. 000 Standard Parallel Port (SPP) mode. The FIFO is reset in this mode. 001 PS/2 Parallel Port mode. In addition to the functions of the SPP mode, this mode has ...
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Bit 3: Read/Write 1 Enables DMA. 0 Disables DMA unconditionally. Bit 2: Read/Write 1 Disables DMA and all of the service interrupts. Writing a logical 1 to this bit does not cause an interrupt. 0 Enables one of the following ...
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NAME TYPE nAck (PeriphClk) This signal indicates valid data driven by the peripheral when I asserted. This signal handshakes with nAutoFd in reverse. Busy (PeriphAck) This signal deasserts to indicate that the peripheral can accept data. In the reverse direction, ...
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Set strobe = 0, causing the nStrobe signal to default to the deasserted state. (c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. (d) Set mode = 011 (ECP Mode) ECP address/RLE bytes ...
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The FIFO threshold is set in LD0 CRO0, bit All data transferred to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used ...
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DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA empties or fills ...
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KEYBOARD CONTROLLER The W83627EHF/EHG/EF/EG KBC (8042 with licensed KB BIOS) circuit is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse and can be used with - ® IBM compatible personal ...
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The input buffer is an 8-bit, write-only register at I/O address 60h or 64h (Default, PnP programmable I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60h sets a flag to indicate a data write; writing to address 64h ...
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COMMAND 20h Read Command Byte of Keyboard Controller 60h Write Command Byte of Keyboard Controller BIT 7 Reserved 6 IBM Keyboard Translate Mode 5 Disable Auxiliary Device 4 Disable Keyboard 3 Reserve System Flag 2 1 Enable Auxiliary Interrupt 0 ...
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COMMAND ABh Interface Test BIT No Error Detected 00 01 Keyboard "Clock" line is stuck low 02 Keyboard "Clock" line is stuck high Keyboard "Data" line is stuck low 03 04 Keyboard "Data" line is stuck high ADh Disable Keyboard ...
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Hardware GATEA20/Keyboard Reset Control Logic The KBC includes hardware control logic to speed-up GATEA20 and KBRESET. This control logic is controlled by LD5-CRF0 as follows: 11.5.1 KB Control Register BIT 7 6 KCLKS1 KCLKS0 Reserved Reserved Reserved NAME KCLKS1, ...
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GATEA20 and KBRESET are controlled by either software or hardware logic, and they are mutually exclusive. Then, GATEA20 and KBRESET are merged with Port92 when the P92EN bit is set. 11.5.2 Port 92 Control Register BIT 7 6 NAME Res. ...
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POWER MANAGEMENT EVENT The PME# (pin 86) signal is connected to the South Bridge and is used to wake up the system from sleeping states. One control bit and four registers in the W83627EHF/EHG/EF/EG are associated ...
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When the W83627EHF/EHG/EF/EG detects the 3VSB voltage rises to “V1”, it then starts a delay – “t” before the rising edge of RSMRST# asserting. If the 3VSB voltage falls below “V2”, the RSMRST# de-asserts immediately. Timing and voltage parameters are ...
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SYMBOL Originally, the t2 timing is between 300 mS to 600 mS, but it can be changed to 200 mS to 300 mS by programming Logical Device A, CR[E6h], bit 3 to “1”. Furthermore, the W83627EHF/EHG/EF/EG provides ...
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For example, if Logical Device A, CR[E6h] bit 2 is set to “0” and bits 2~1 are set to “10”, the range of t2 timing is from 396(300 + 96 596(500 + 96) mS. W83627EHF/EF, W83627EHG/EG Publication Release ...
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SERIALIZED IRQ The W83627EHF/EHG/EF/EG supports a serialized IRQ scheme. This allows a signal line to be used to report the parallel interrupt requests. Since more than one device may need to share the signal serial SERIRQ signal, an open ...
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START FRAME PCICLK 1 START SER IRQ 2 Drive Source IRQ1 Host Controller H=Host Control SL=Slave Control Note: 1. The Start Frame pulse can be 4-8 clocks wide. 2. The first clock of Start Frame is ...
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SERIRQ SAMPLING PERIODS IRQ/DATA FRAME SIGNAL SAMPLED 1 IRQ0 2 IRQ1 3 SMI# 4 IRQ3 5 IRQ4 6 IRQ5 7 IRQ6 8 IRQ7 9 IRQ8 10 IRQ9 11 IRQ10 12 IRQ11 13 IRQ12 14 IRQ13 15 IRQ14 16 IRQ15 17 ...
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Stop Frame After all IRQ/Data Frames have completed, the host controller will terminates SERIRQ with a Stop frame. Only the host controller can initiate the Stop Frame by driving SERIRQ low for clocks. If the Stop ...